• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 29 subscribers
  • Views 1163 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Complex SPI, DMA, CRC, RTI, FIQ integration scenario

Tony Morrell
Genius 4130 points

 

I have a complex TMS570 SPI problem which I would appreciate some advice on.

Requirements:

My SPI Master transmits a 9-word (i.e. 9*16=144-bit) message. The first 8 words contain control data, the last word contains a CRC of the 8 data words. I am using one transfer group within my SPI, and only 9 of the available 128 RXRAM buffers. All CRCs are generated by the TMS570 CRC module. One 9-word message is transmitted every 62.4us.

My SPI Slave must receive and process this data at high priority, it is to be made available to another high priority task, driven by ADC FIQ. As a preference, the SPI data recieve must not delay the ADC-FIQ task. There are several requirements on the received SPI data:

  1. It must be CRC checked before it can be made available to the ADC-FIQ task.
  2. Its time of receipt must be recorded for that message to allow ADC-FIQ to accurately determine its age (it contains time dependant control data).
  3. As well as being made available to the ADC-FIQ task, it must be buffered for access by a slow task running at 1ms nominal. This means that at least (1000/62.4)=17, and preferably 32, messages must be buffered.

At present:

  1. I have an SPI FIQ configured to process the received data. This will obviously impact the ADC-FIQ task, and I have another forum question open to try and discover a means of prioritising my two FIQs (see http://e2e.ti.com/support/microcontrollers/tms570/f/312/t/102102.aspx). This SPI-FIQ ISR performs received CRC and circular message buffer management 'manually', copying data from SPI RXRAM to uP internal RAM with circular buffer head and tail pointer management. It must also calculate the CRC of the data sent back to the SPI Master (on SOMI). This technique provides the data exactly as I would want for both ADC-FIQ and slow task processing, but it takes some 9.5us to perform this task. This is way too long, I need something more like 1us or 2us.
  2. I have an RTI capture on SPI interrupt configured to satisfy requirement 2 above.

Within my code, I have commented out both CRC calculations and copy from SPI RXRAM to uP internal RAM to determine the time required by these intensive manipulations. This reduces the SPI_FIQ ISR run time to 1.5us.

I really need to integrate some DMA mechanism into this procedure, and potentially make better use ofthe spare RXRAM buffers, instead of the 9 I am currently using.

Questions:

  1. Can I get my SPI Slave to automatically receive multiple message data into contiguous RXRAM so I could implement a circular buffer within it (it would hold 14 9-word message, so pretty close to my 17-word minimum requirement)?
  2. Or, can I use DMA to write SPI received data directly to a circular buffer (I couldn't work out how to implement DMA write to multi-word 'frames' in this circular fashion)?
  3. Could I use DMA to feed into the CRC determination, preferably at the same time as DMA transfer to uP RAM?
  4. Can I actually drive more than one DMA request from SPI receive?
  5. Given this potential DMA automation, I think my ADC_FIQ task would necessarily have to perform the CRC verification, i.e. check the CRC in the received SPI message against that determined by the uP CRC module. Would it be possible to integrate the CRC module auto-mode signature verification or would I most likely need to use the semi-cpu-mode signature verification? 

Regards, Tony.