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Hello,
As described in the manual,Threshold Interrupt Flag can be cleared by writing a 1,I want to know if the Threshold Interrupt Control Register will also be reset to he originally configured threshold count?
Thanks.
No, writing 1 to threshold interrupt flag won't reset the threshold counter. The counter gets back to its original value only when the memory region is emptied.
The threshold register behaves like a down-counter, which decrements each time the ADC writes a conversion result to this group’s memory. This counter is incremented each time the application program reads a conversion result from the results’ memory by accessing the FIFO queue. Simultaneous read (by application program) and write (by ADC module) operations from the group’s results’ memory leave the threshold counter unchanged.
Whenever the threshold counter transitions from +1 to 0, it sets the group’s threshold interrupt flag, and the CPU is interrupted if the group’s threshold interrupt is enabled.
The CPU is expected to clear the interrupt flag after reading the conversion results from the memory.
Hi QJ Wang,
Assume the conversion group is configured for continuous conversion and allows overwrite.The number of channels selected for conversion is 23,the number of memory buffers is 22,and the threshold interrupt counter is 23,I want to know when 22 results are written into result ram,the 23rd result overwrite buffer0,will the counter from 1 to 0 or reset from 1 to 23?
Thanks.
Is this your real application: using 22 buffers for 23 ADC channels, and the counter is 23?
Why don't you use more buffers for this ADC conversion group? The ADC memory supports up to 64 words.
When the ADC module tries to store more conversion results to a group’s results’ memory which is already full:
If the OVR_RAM_IGN bit is set, the ADC module ignores the contents of the group’s results’ memory and wraps around to overwrite the memory with the results of new conversions.
If the OVR_RAM_IGN bit is not set, then the application has to read out the group’s results’ memory upon an overrun condition; only then can the ADC continue to write new results to the memory.
Did you get interrupt using this configuration? Please increase the number of buffers, your configuration makes thing complex.
Since it has been a long time since the last activity on this thread, I would assume that your issue has been resolved or it is not longer relevant to you so I will close this thread. If there are any lingering issues or new questions, I encourage you to open a new thread so that we may address them.