TMS570LC4357: PBIST - FSRA and FSRDL Register

Hi,

The first address failure is sequential within the group under test noting that RGS and RDS will also be sequential corresponding to the 64 bit word located at the address.

RGS = 2 , RDS = 1 --> means that the error happens in ADC memory. 

Thanks for the reply.

It is still a bit unclear to me.. Where do I get the info about ADC Memory? Table 2.5 in the Reference Manual indicates AWM1 for (RGS=2, RDS=1)

And could you give some info about the second part of the question about FSRDL0? 

AxelanderS said:

I am currently confused by FSRA0 being 0 as I would assume it to give me an Address in case of a failure and FSRDL0 as I do not fully understand what this Value is actually indicating or what it means?

For testing purposes I have tried to run the test on two boards but both of them give me the exact same result except for the FSRDL0 Register. FSRDL0 actually changed due to the change of boards and even on the same board it seems to be a little different every time the test is run. 

So my question would be, what does FSRDL0 (FSRDL1) actually tell me and could I assume to have some flaws in my configuration as it seems to be a little odd that two boards indicate the exact same outcome except for the Failure Data and the Address being 0? 

Thanks!

The RGS and RDS refer to physical instances of memory arrays, but I don't have the physical to logical mapping. Even if we know which group and which array returned data (RDS), we still don't know the exact location in the memory.

FSRA0 is the memory address of the first failure on port 0. If FSRA0=0, the error is probably happened at the beginning of the ADC memory.

Can you perform for ADC memory only instead of all the memories (single-port and dual-port) to see if you get the error in the same location?

Hey QJ,

Table 2-5 of the Ref. Manual indicates that RDS=2 and RGS=1 maps to Memory Group 5 (AWM1). If I run the Test only for this specific memory group I get the following results:

RDS=1 / RGS=1

FSRA0 = 0

FSRDL0 = 2

FSRC0 = 4

I have run the test on two different Eval Boards and the results for the AWM1 only test are exactly the same.

What information can I get out of this?

The test for ALL groups still only differs in FSRDL0 being either 3F65D or 1E7BF but both indicate the same RGS=2, RDS=1, FSRC0=3, FSRA0=0 values.

It feels strange to me, that both boards have such similar results...

Thanks!

TMS570LC43x_RefMan.pdf

I am using this Reference Manual Version

I just did a test, do not see the issue:

This is my test case:

/* PBIST test on RAMs */
void PBIST_SelfTest(uint32 raminfoH, uint32 raminfoL, uint32 algomask)
{
volatile uint32 i = 0U;

/* PBIST ROM clock frequency = HCLK frequency /2 */
/* Disable memory self controller */
systemREG1->MSTGCR = 0x00000105U;

/* Disable Memory Initialization controller */
systemREG1->MINITGCR = 0x5U;

/* Enable PBIST controller */
systemREG1->MSINENA = 0x1U;

/* Enable memory self controller */
systemREG1->MSTGCR = 0x0000010AU;

/* wait for 64 VBUS clock cycles at least, based on GCLK to VCLK ratio */
for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }

/* USER CODE BEGIN (18) */
/* USER CODE END */

/* Enable PBIST clocks and ROM clock */
pbistREG->PACT = 0x1U;

/* Select all algorithms to be tested */
pbistREG->ALGO = algomask;

/* Select RAM groups */
pbistREG->RINFOL = raminfoL;

/* Select all RAM groups */
pbistREG->RINFOU = raminfoH;

/* ROM contents will not override RINFOx settings */
pbistREG->OVER = 0x0U;

/* Algorithm code is loaded from ROM */
pbistREG->ROM = 0x3U;

/* Start PBIST */
pbistREG->DLR = 0x14U;

}