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TMS570LC4357: TMS570LC43 SCI interrupt issue -

anil pande
Prodigy 80 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hi,

I am using Halcogen to generate peripheral code for SCI evaluation as described in the video from TI. 

The only difference, I have selected  Microcontroller with FreeRTOS.

Observation - with all confirmed setup for reception, unable to get hit at sci_notification interrupt  indicating character is received while debugging.

Please guide to resolve this issue.

Thanks in advance!

  • 0
    TI__Guru**** 198766 points

    Hi Anil,

    Are you able to get the SCI interrupt if the freeRTOS scheduler is not started?

  • 0
    Prodigy 80 points

    Hi QJ Wang,

    Thanks! I will check.

    I have another query. I used halcogen example code for CAN evaluation. It works well in internal loopback mode.

    When I tried to check normal CAN working by connecting external CAN bus using CAN transceiver, unable to receive data.

    Request to advice. Thanks in advance - Anil 

  • 0 in reply to anil pande
    TI__Guru**** 198766 points

    Hi Anil,

    Would you please open a new thread for this CAN question? Thanks

  • 0 in reply to QJ Wang
    TI__Guru**** 198766 points

    Are you able to get the SCI interrupt if the freeRTOS scheduler is not started?

  • 0 in reply to anil pande
    Prodigy 80 points

    Hi QJ Wang,

    I am not able to get SCI interrupt when freeRTOS schedular is not started.

    Please advice.

    Thanks

  • +1 in reply to anil pande
    TI__Guru**** 198766 points

    Hello Anil,

    The ARM architecture defines the exception vectors as follows:

    Address Exception
    0x00000000 Reset
    0x00000004 Undefined instruction
    0x00000008 Software Interrupt
    0x0000000C  Prefetch Abort
    0x00000010 Data Abort
    0x00000014 Reserved for future use
    0x00000018 IRQ
    0x0000001C FIQ

    Basically these are the exceptions that the CPU can "trap". The exception vectors are used by the application to branch to the appropriate exception handling routines. The sys_intvecs.asm defines these branch instructions in a section called .intvecs. The linker command file then maps this .intvecs section to start at address 0x00000000.

    Please refer the CPU technical reference manual for more information on these exceptions.

    There are several "gates" before an interrupt request gets to the CPU:

    1. The module that generates an interrupt request has a register to enable each interrupt that it can generate.
    2. The Vectored Interrupt Manager (VIM) has registers to allow an interrupt request from a module to be forwarded to the CPU as per the priority scheme (lower channel number first).
    3. Finally the CPU itself must be configured to respond to the interrupt requests forwarded by the VIM (IRQ or FIQ).

    Please check your code to make sure that the interrupt is enabled:

    1. sciREGx->SETINT

    2. SCI channel in VIM table is selected:

    3. IRQ is enabled: _enable_IRQ();