TMS570LC4357: Regarding "Register Soft Error"

Hi Sho,

Please refer to those links:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/909079/tms570lc4357-register-soft-error-reaction-on-multi-bit-flip/3363146?tisearch=e2e-sitesearch&keymatch=soft%2525252525252520error#3363146

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/512091/esm1-90---sys---register-soft-error?tisearch=e2e-sitesearch&keymatch=soft%2525252520error%2525252520AND%2525252520register#

Hello QJ-san,

Thank you for your reply.

I read your recommendation thread, and I have additional questions.

I think two threads are disagreement.

(Thread name : Register Soft Error / Reaction on Multi-bit flip)

Each bit of these high-integrity register fields are actually implemented as a set of 5 flops. This implementation supports auto-correction for up to 2 bits of errors. If there are more than 2 errors within these 5 flops, then it is detected as an uncorrectable error and signaled to ESM channels 88 through 90.

(Thread name : ESM1.90 - SYS - Register Soft Error)

These registers from the programmer model perspective are single bits but in actual implementation they are multi-bits. For example, the CPURSTCR has only one visible bit from a programmer's model. This bit is used to generate a CPU reset. However, there are actually several physical bits implemented with self-correction logic such that when one bit flipped it will signal an error to the ESM and also correct it back. 

(SPNU563A Sec 2.5.1.41)

NOTE: The register bits in CPURSTCR are designated as high-integrity bits and have been
implemented with error-correcting logic such that each bit, although read and written as a
single bit, is actually a multi-bit key with error correction capability. As such, single-bit flips
within the “key” can be corrected allowing protection of the system as a whole. An error
detected is signaled to the ESM module.

Which description is correct?

ESM 1.88 to 1.90 is generated when corrected single bit error, is it correct? 

Thanks,

Sho

Hi QJ-san,

Thank you for your support.

I understood as a following about operated the high-integrity bits.

In this figure, Multi-bit key will have 5-bit into SYS Module Core, I think this 5-bit means 5 flops in your reply.

So, Register soft error is occurred when detected more than 2-bit error into accessing each 5-bit to CDDIS register.

Is this image correct?
Please advice me.

Thanks,

Sho

Hello QJ-san,

I'm sorry, maybe my inserted image is broken.

I send as a following image again.

Thanks,

Sho