UCD3138LLCHBFirmware-1.2 turn on delay

user5316778

There is a delay interval between 3.3VCC ready and first pulse of gate drive signal of primary side (DPWM0A, DPWM0B).

But this delay interval is very long, approximately 120ms, and how to reduce this delay interval?

Note: The soft-start time and delay_cycle are 10ms and 0.

+1 Sean Xu over 4 years ago

Hello,

Did you test Ti LLC EVM? Did you see the delay on the board?

Thanks,

Sean

+1 user5316778 over 4 years ago in reply to Sean Xu

Reduce count_end？

+1 Sean Xu over 4 years ago in reply to user5316778

I don't understand what you mean.

I suspect the delay is caused by bias start up, and you can try to reduce the delay of bias.

+1 user5316778 over 4 years ago in reply to Sean Xu

This question is solved.

Count_end =1000 needs to be reduced.

+1 Sean Xu over 4 years ago in reply to user5316778

Thanks for updating

Arm-based microcontrollers forum