TMS570LS1224: Pin status after a non-PORST reset event

Marcus Coxon

In order to establish a safety case for our design, I would like to know what the status of the pins is after a reset that was not initiated by the assertion of the nPORRST pin (SYSESR[15], PORST=1).

The SPNS190B doc, section 4.3 defines the status for nPORRST related resets but the behaviour in other cases, appears to be undefined.

In particular, I am concerned re the following sets

GIOA[]
N2HET1[]

over 5 years ago

+1 QJ Wang over 5 years ago

TI__Guru**** 201386 points

Hi Marcus,

The TRM register description includes the bit-field reset values. This typically refers to warm reset (system reset nRST). For example, the default value in GIO DIR register shows that the GIO pins is configured as INPUT after RESET (warm reset).

Any bit-field that is only reset by cold reset (power-on-reset nPORRST) is explicitly specified as such. For example, ESM status registers are only reset by cold reset.

0 Marcus Coxon over 5 years ago in reply to QJ Wang

Prodigy 250 points

Hi QJ, thanks for your info.

Marcus

Arm-based microcontrollers

Arm-based microcontrollers forum

TMS570LS1224: Pin status after a non-PORST reset event