Part Number: SIMPLELINK-MSP432-SDK
Hi,
We are having a problem with the STE signal in 4 wire mode running the SPI at 12 MHz, the MCLK at 24MHz and SMCLK at 12 MHz.
Our setup is as follows:
- Custom board with the MSP432P4111 and an external flash IS25LP032 from ISSI.
- No more devices connected to the SPI bus.
- Code Composer Studio version 10.2.0.00009, with Simplelink SDK version 3_40_01_02 and TI v20.2.5.LTS compiler.
- The application calls SPI.h functions of the TI SPI driver (pointing to SPIMSP432DMA.c functions).
What we see in the logic analyzer is that after eight SPI clock pulses the next clock pulse (9th) is stretched and at the same time the STE signal goes high in some cases, which results in a loss of communication with the external flash.
If we decrease the SPI frequency to 6 MHz, with the MCLK at 24MHz and SMCLK at 12 MHz it works fine.
Also, if we have SPI frequency at 12 MHz, the MCLK at 48MHz and SMCLK at 24 MHz it also works fine.
We have reproduced this in an attached example project that tries to read the flash ID register and then writes a page, reads it and checks the read values in a loop.
The following image shows the error: The MSP432 writes 0x9F (JEDEC_IC command) in the MOSI line, and it expect to read 3 bytes corresponding to the flash ID of the chip (0x9D, 0x60, 0x16), but only receives the first byte (0x9D).
And the following is the expected result, captured with SPI at 6MHz, in which the STE signal remains low for all the duration of the transfer, and the clock pulses are not stretched:
- Why does the STE signal go high in the middle of the transaction at 12 MHz, and how can we resolve this error?
We believe that the clock stretching happens due to the DMA interrupt having to pass the byte to/from the SPI bus to memory, is that true?
Thank you very much for your kind help,
Alvaro
