Other Parts Discussed in Thread: TMS570LC4357
I have an EMIF-interface on a TI MCU, which is configured with an 8bit external width data bus; the interface is asynchronous SRAM Normal mode. But the MCU is interfacing an FPGA, and I am only interested in the decoding of EMIF access, i.e., the HW-view. The question is the following:
Is it possible to read or write a single 32bit word to a physical 8bit EMIF-port with a single operation, so that the actual action on the port is a sequence of 4 read/writes (i.e., activations of nRW and/or nCS, and byte address BA[1..0] incremented from 0..3 or maybe decremented);
(byte enable signals are probably also updated, but this is not used).
All illustrations in SPRU971e and Ref Manual to TMS570LC4357 16/32-Bit RISC Flash Microcontroller only show one transaction.
OR
Is it so, that with 8bit wide EMIF interface, ONLY byte access is possible, and a 32bit wide reading/writing has to be performed as 4 individual operations. In my case this will be unfortunate, because SW guys then have to prevent for example interrupts from disrupting the 4 consecutive operations.
