I have setup a baremetal driver for the qspi MIBSPI5 of the tms570 chip. However, you will notice there is a delay in between each 16 bit packets, as seen in the below screenshot of my logic analyser. The delay in between each clock burst is of about 100ns for a 25MHz clock. i send a burst of 128 packets of 16 bits on the four data lines.
The WDEL and DFSEL bits of every buffer in the txram of mibspi5 is set to 0, i have checked directly in the ram. The WDELAY bits 24 to 31 of the SPIFMT0 register are set to 0, and all bits of the SPIDELAY register are 0,i have validated directly in the registers using my debugger. What am I missing, why is this delay present? I would expect that i could send data continuously without a pause in the clk line?
1. CS (not functionnal, will solve seperately)
2-5. mosi 0-3
Thank you very much for any help you can provide!