Hello,
This is question regarding PBIST Algorithm.
We are now testing the Self-test function of TMS570 MCU on the evaluation board.
Regarding PBIST Algorithm, We already read PBIST Algorithm Mapping on Table 2-6 of SPNU563A, but this document was only explained about March13 Algorithm.
The sl_type.h part of Safety Lib include as a following several algorithm;
#if defined(_TMS570LC43x_) || defined(_RM57Lx_)
#define PBISTALGO_TRIPLE_READ_SLOW_READ (uint32)0x00000001u /**<TRIPLE_READ_SLOW_READ for PBIST and STC ROM*/
#define PBISTALGO_TRIPLE_READ_FAST_READ (uint32)0x00000002u /**<TRIPLE_READ_SLOW_READ for PBIST and STC ROM*/
#define PBISTALGO_MARCH13N_2PORT (uint32)0x00000004u /**< March13 N Algo for 2 Port mem --- BASELINE TEST ALGO with HIGHEST OVERALL COVERAGE */
#define PBISTALGO_MARCH13N_1PORT (uint32)0x00000008u /**< March13 N Algo for 1 Port mem --- BASELINE TEST ALGO with HIGHEST OVERALL COVERAGE */
#define PBISTALGO_DOWN2_1PORT (uint32)0x00000010u /**< */
#define PBISTALGO_DOWN2_2PORT (uint32)0x00000020u /**< */
#define PBISTALGO_MARCH_DIS_INC_1PORT (uint32)0x00000040u /**< */
#define PBISTALGO_MARCH_DIS_INC_2PORT (uint32)0x00000080u /**< */
#define PBISTALGO_MARCH_DIS_DEC_1PORT (uint32)0x00000100u /**< */
#define PBISTALGO_MARCH_DIS_DEC_2PORT (uint32)0x00000200u /**< */
#define PBISTALGO_MARCH_DIS_INC_1PORT_1 (uint32)0x00000400u /**< */
#define PBISTALGO_MARCH_DIS_INC_2PORT_1 (uint32)0x00000800u /**< */
#define PBISTALGO_MARCH_DIS_DEC_1PORT_1 (uint32)0x00001000u /**< */
#define PBISTALGO_MARCH_DIS_DEC_2PORT_1 (uint32)0x00002000u /**< */
#define PBISTALGO_MAP_COLUMN_1PORT (uint32)0x00004000u /**< Map Column algo (to identify bit line senstivities) for 1 Port memory */
#define PBISTALGO_MAP_COLUMN_2PORT (uint32)0x00008000u /**< Map Column algo (to identify bit line senstivities) for 2 Port memory */
#define PBISTALGO_PRECHARGE_1PORT (uint32)0x00010000u /**< Pre-Charge algo to exercise pre-charge capability for 1 port memory */
#define PBISTALGO_PRECHARGE_2PORT (uint32)0x00020000u /**< Pre-Charge algo to exercise pre-charge capability for 2 port memory */
#define PBISTALGO_FLIP10_1PORT (uint32)0x00040000u /**< */
#define PBISTALGO_FLIP10_2PORT (uint32)0x00080000u /**< */
#define PBISTALGO_DTXN2_1PORT (uint32)0x00100000u /**< Global column decode logic algo for 1 Port memories*/
#define PBISTALGO_DTXN2_2PORT (uint32)0x00200000u /**< Global column decode logic algo for 2 Port memories*/
#define PBISTALGO_PMOS_OP_SLICE1_1PORT (uint32)0x00400000u /**<pmos open slice1 for 1port memories*/
#define PBISTALGO_PMOS_OP_SLICE1_2PORT (uint32)0x00800000u /**<pmos open slice1 for 2port memories*/
#define PBISTALGO_PMOS_OP_SLICE2_2PORT (uint32)0x01000000u /**<pmos open slice2 for 2port memories*/
#endif
We could check operating each algorithm based on Safety Lib, but these are not explained anywhere of SPNU563A, SPNS253A and SPNU540A.
Are there other documents or information explained about details of these algorithm?
Thanks,
Sho
