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TM4C129XNCZAD: Boot loader example code for above part no.

Rajesh Varma
Intellectual 300 points
Part Number: TM4C129XNCZAD


Dear sir,

I have stellaris old board of LM3s9B96 and having example code of boot_serial,boot_demo1,boot_demo2 .Boot loader working perfect for above board.

I n similar way I need Boot loader code for TM4C129XNCZAD part no.

I have TM4C129xdevelopment board on which I can check it before implement in my actual project.

The example package don't have above example code for same.

I having example code for TM4C1294L and it is not matching with my board.

So please share example code of Boot loade for above development board for above part no.

  • 0
    TI__Guru**** 191906 points

    Hi,

      You can use the same boot_serial example for TM4C1294XL on TM4C129x development board because the UART0RX/UART0TX pin mapping is the same. UART0RX -> PA0 and UART0TX -> PA1. 

    The bl_config.h file has directives that configure UART pins and it will work on both LaunchPad as well as development board. 

    //*****************************************************************************
    //
    // Selects the baud rate to be used for the UART.
    //
    // Depends on: UART_ENABLE_UPDATE, CRYSTAL_FREQ
    // Exclusive of: UART_AUTOBAUD
    // Requires: None
    //
    //*****************************************************************************
    #define UART_FIXED_BAUDRATE 115200

    //*****************************************************************************
    //
    // Selects the clock enable for the UART peripheral module
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UARTx_BASE
    //
    //*****************************************************************************
    #define UART_CLOCK_ENABLE SYSCTL_RCGCUART_R0

    //*****************************************************************************
    //
    // Selects the base address of the UART peripheral module
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_CLOCK_ENABLE
    //
    //*****************************************************************************
    #define UARTx_BASE UART0_BASE

    //*****************************************************************************
    //
    // Selects the clock enable for the GPIO corresponding to UART RX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_RXPIN_BASE, UART_RXPIN_PCTL and UART_RXPIN_POS
    //
    //*****************************************************************************
    #define UART_RXPIN_CLOCK_ENABLE SYSCTL_RCGCGPIO_R0

    //*****************************************************************************
    //
    // Selects the base address for the GPIO corresponding to UART RX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_PCTL and UART_RXPIN_POS
    //
    //*****************************************************************************
    #define UART_RXPIN_BASE GPIO_PORTA_BASE

    //*****************************************************************************
    //
    // Selects the port control value for the GPIO corresponding to UART RX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_BASE and UART_RXPIN_POS
    //
    //*****************************************************************************
    #define UART_RXPIN_PCTL 0x1

    //*****************************************************************************
    //
    // Selects the pin number for the GPIO corresponding to UART RX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_BASE and UART_RXPIN_PCTL
    //
    //*****************************************************************************
    #define UART_RXPIN_POS 0

    //*****************************************************************************
    //
    // Selects the clock enable for the GPIO corresponding to UART TX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_TXPIN_BASE, UART_TXPIN_PCTL and UART_TXPIN_POS
    //
    //*****************************************************************************
    #define UART_TXPIN_CLOCK_ENABLE SYSCTL_RCGCGPIO_R0

    //*****************************************************************************
    //
    // Selects the base address for the GPIO corresponding to UART TX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_TXPIN_CLOCK_ENABLE, UART_TXPIN_PCTL and UART_TXPIN_POS
    //
    //*****************************************************************************
    #define UART_TXPIN_BASE GPIO_PORTA_BASE

    //*****************************************************************************
    //
    // Selects the port control value for the GPIO corresponding to UART TX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_TXPIN_CLOCK_ENABLE, UART_TXPIN_BASE and UART_TXPIN_POS
    //
    //*****************************************************************************
    #define UART_TXPIN_PCTL 0x1

    //*****************************************************************************
    //
    // Selects the pin number for the GPIO corresponding to UART TX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_TXPIN_CLOCK_ENABLE, UART_TXPIN_BASE and UART_TXPIN_PCTL
    //
    //*****************************************************************************
    #define UART_TXPIN_POS 1

    //*****************************************************************************

  • 0 in reply to Charles Tsai
    Intellectual 300 points

    Dear Charles,

    I have attached the bootloader_file which i have userd.

    I have dump the boot loader @ 0x0000 location  which consist of application address 0x4000

    I dump the code @0x4000 using debugger   and device boot up properly.

    Now i am dumping the another code through serial @ baud rate 9600 which is defined in code but getting error message.

    The com port is right com 17 i have checked in device manager.

    8345.boot_serial.zip

  • 0 in reply to Rajesh Varma
    TI__Guru**** 191906 points

    You need to change the bootloader UART baud rate to match the baudrate in LM flash programmer. In the bl_config.h you have 115200 while in LM flash programmer you choose 9600. It will not work. You either rebuild the booloader for 9600 baud or change the LM flash programmer 115200.

    //*****************************************************************************
    //
    // Selects the baud rate to be used for the UART.
    //
    // Depends on: UART_ENABLE_UPDATE, CRYSTAL_FREQ
    // Exclusive of: UART_AUTOBAUD
    // Requires: None
    //
    //*****************************************************************************
    #define UART_FIXED_BAUDRATE 115200

  • 0 in reply to Charles Tsai
    Intellectual 300 points

    Dear Charles,

    Thanks ,Its working Now. 

    Its working with UART0 what changes  need to be do for  UART1  in attached BL_config.h.

    My ultimate requirement with UART1

    Please find the attached BL_config.h

    8204.bl_config.h

  • +1 in reply to Rajesh Varma
    TI__Guru**** 191906 points

    Hi,

      Try this change. 

    //*****************************************************************************
//
// Selects the baud rate to be used for the UART.
//
// Depends on: UART_ENABLE_UPDATE, CRYSTAL_FREQ
// Exclusive of: UART_AUTOBAUD
// Requires: None
//
//*****************************************************************************
#define UART_FIXED_BAUDRATE     115200

//*****************************************************************************
//
// Selects the clock enable for the UART peripheral module
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UARTx_BASE
//
//*****************************************************************************
#define UART_CLOCK_ENABLE     SYSCTL_RCGCUART_R1

//*****************************************************************************
//
// Selects the base address of the UART peripheral module
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_CLOCK_ENABLE
//
//*****************************************************************************
#define UARTx_BASE     UART1_BASE

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to UART RX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_RXPIN_BASE, UART_RXPIN_PCTL and UART_RXPIN_POS
//
//*****************************************************************************
#define UART_RXPIN_CLOCK_ENABLE     SYSCTL_RCGCGPIO_R1

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to UART RX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_PCTL and UART_RXPIN_POS
//
//*****************************************************************************
#define UART_RXPIN_BASE     GPIO_PORTB_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to UART RX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_BASE and UART_RXPIN_POS
//
//*****************************************************************************
#define UART_RXPIN_PCTL     0x1

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to UART RX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_BASE and UART_RXPIN_PCTL
//
//*****************************************************************************
#define UART_RXPIN_POS     0

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to UART TX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_TXPIN_BASE, UART_TXPIN_PCTL and UART_TXPIN_POS
//
//*****************************************************************************
#define UART_TXPIN_CLOCK_ENABLE     SYSCTL_RCGCGPIO_R1

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to UART TX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_TXPIN_CLOCK_ENABLE, UART_TXPIN_PCTL and UART_TXPIN_POS
//
//*****************************************************************************
#define UART_TXPIN_BASE     GPIO_PORTB_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to UART TX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_TXPIN_CLOCK_ENABLE, UART_TXPIN_BASE and UART_TXPIN_POS
//
//*****************************************************************************
#define UART_TXPIN_PCTL     0x1

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to UART TX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_TXPIN_CLOCK_ENABLE, UART_TXPIN_BASE and UART_TXPIN_PCTL
//
//*****************************************************************************
#define UART_TXPIN_POS     1