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RM57L843: RTI timer period offset issue

Cherry Zhou
Mastermind 22235 points
Part Number: RM57L843
Other Parts Discussed in Thread: HALCOGEN

The RTI module is configured in HALCOGEN as follows:

3 timing interrupts are generated with counter 0: 1 ms (compare0), 4 ms (compare1), and 10 ms (compare2). Counter 1, compare 3 cycle maximum (0xFFFFFFFFFF) is also used to monitor the cycles of the 1 ms and 4 ms timer interrupts mentioned above. By reading the tick of Compare3, the function is rtiGetCurrentTick (compare3), calculates the difference between the two interrupts of this return value to get the period, and records the maximum and minimum values for the above period.

Issue:

The 10 ms task performs more (the function performs more), the 1 ms and 4 ms timing cycles are offset larger, and there is no interrupt off and re-enable in 10 ms.

The customer would like to know what's the possible reason for that.

Thanks!

Best Regards,

Cherry Zhou

  • 0
    TI__Guru**** 199096 points

    Hi Cherry,

    Do you mean the customer got more compare 2 interrupt, and less interrupt from compare1 and compare 0? The customer can declare 3 global variables (for example cnt0, cnt1, and cnt2) to count the number of the interrupts from compare 0/1/2.

    void rtiNotification(rtiBASE_t *rtiREG, uint32 notification)
    {
         /* enter user code between the USER CODE BEGIN and USER CODE END. */
         /* USER CODE BEGIN (12) */

         if (notification == rtiCOMPARE0)

              cnt0++;

         if (notification == rtiCOMPARE1)

              cnt1++;

         if (notification == rtiCOMPARE2)

              cnt2++;

         /* USER CODE END */
    }

    I don't know how the customer method works.