HAL Code Generator Version 04.07.01
CCS Version 10.4.0.00006
I extended the given example example_mibspiDMA.c with 2 transfer groups. Unfortunately the transfer of the received data for the second group from mibSPI1 to RAM location via DMA does not work. I defined 2 transfer groups in the HAL Code Generator, each having 64 buffers. After that I generated the code with HAL Code Generator and modified the example module example_mspiDMA.c. Please find below the content of the modified example_mibspiDMA.c. Do you have an idea what is wrong in this code. The transfer of transfer group 0 works fine.
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "HL_sys_common.h"
/* USER CODE BEGIN (1) */
#include "HL_mibspi.h"
#include "HL_sys_dma.h"
/* example data Pattern configuration */
#define D_SIZE 64
void loadDataPattern(uint32 psize, uint16* pptr);
void mibspiEnableInternalLoopback(mibspiBASE_t *mibspi);
void dmaConfigCtrlPacket(uint32 sadd,uint32 dadd,uint32 dsize);
void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel);
#pragma SET_DATA_SECTION(".sharedRAM")
uint16 TG0_TXDATA[D_SIZE]; /* transmit buffer in sys ram */
uint16 TG0_RXDATA[D_SIZE]= {0}; /* receive buffer in sys ram */
uint16 TG1_TXDATA[D_SIZE]; /* transmit buffer in sys ram */
uint16 TG1_RXDATA[D_SIZE]= {0}; /* receive buffer in sys ram */
#pragma SET_DATA_SECTION()
g_dmaCTRL g_dmaCTRLPKT1, g_dmaCTRLPKT2; /* dma control packet configuration stack */
/* USER CODE END */
/** @fn void main(void)
* @brief Application main function
* @note This function is empty by default.
*
* This function is called after startup.
* The user can use this function to implement the application.
*/
/* USER CODE BEGIN (2) */
/* USER CODE END */
void main(void)
{
/* USER CODE BEGIN (3) */
/* - creating a data chunk in system ram to start with ... */
loadDataPattern(D_SIZE, &TG0_TXDATA[0]);
loadDataPattern(D_SIZE, &TG1_TXDATA[0]);
/* - initializing mibspi - enabling tg 0 , length 127 (halcogen file)*/
mibspiInit();
/* - enabling loopback ( this is to emulate data transfer without external wires */
mibspiEnableInternalLoopback(mibspiREG1);
/* - configuring dma control packets TG0 */
g_dmaCTRLPKT1.SADD = (uint32)TG0_TXDATA; /* source address */
g_dmaCTRLPKT1.DADD = (uint32)&(mibspiRAM1->tx[0].data); /* destination address */
g_dmaCTRLPKT1.CHCTRL = 3+1; /* channel control */
g_dmaCTRLPKT1.FRCNT = 1; /* frame count */
g_dmaCTRLPKT1.ELCNT = D_SIZE; /* element count */
g_dmaCTRLPKT1.ELDOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT1.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT1.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.PORTASGN = PORTA_READ_PORTB_WRITE;
g_dmaCTRLPKT1.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT1.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT1.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT1.ADDMODEWR = ADDR_OFFSET; /* address mode write */
g_dmaCTRLPKT1.AUTOINIT = AUTOINIT_ON; /* autoinit */
g_dmaCTRLPKT2.SADD = (uint32)&(mibspiRAM1->rx[0].data); /* source address */
g_dmaCTRLPKT2.DADD = (uint32)TG0_RXDATA; /* destination address */
g_dmaCTRLPKT2.CHCTRL = 2+1; /* channel control */
g_dmaCTRLPKT2.FRCNT = 1; /* frame count */
g_dmaCTRLPKT2.ELCNT = D_SIZE; /* element count */
g_dmaCTRLPKT2.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT2.ELSOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT2.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT2.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT2.PORTASGN = PORTB_READ_PORTA_WRITE;
g_dmaCTRLPKT2.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT2.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT2.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT2.ADDMODERD = ADDR_OFFSET; /* address mode read */
g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT2.AUTOINIT = AUTOINIT_ON; /* autoinit */
/* upto 32 control packets are supported. */
/* - setting dma control packets */
dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT2);
dmaSetCtrlPacket(DMA_CH1,g_dmaCTRLPKT1);
/* - setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH0, DMA_HW);
dmaSetChEnable(DMA_CH1, DMA_HW);
/* - configuring dma control packets TG1 */
g_dmaCTRLPKT1.SADD = (uint32)TG1_TXDATA; /* source address */
g_dmaCTRLPKT1.DADD = (uint32)&(mibspiRAM1->tx[64].data); /* destination address */
g_dmaCTRLPKT1.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT1.FRCNT = 1; /* frame count */
g_dmaCTRLPKT1.ELCNT = D_SIZE; /* element count */
g_dmaCTRLPKT1.ELDOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT1.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT1.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.PORTASGN = PORTA_READ_PORTB_WRITE;
g_dmaCTRLPKT1.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT1.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT1.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT1.ADDMODEWR = ADDR_OFFSET; /* address mode write */
g_dmaCTRLPKT1.AUTOINIT = AUTOINIT_ON; /* autoinit */
g_dmaCTRLPKT2.SADD = (uint32)&(mibspiRAM1->rx[64].data); /* source address */
g_dmaCTRLPKT2.DADD = (uint32)TG1_RXDATA; /* destination address */
g_dmaCTRLPKT2.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT2.FRCNT = 1; /* frame count */
g_dmaCTRLPKT2.ELCNT = D_SIZE; /* element count */
g_dmaCTRLPKT2.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT2.ELSOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT2.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT2.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT2.PORTASGN = PORTB_READ_PORTA_WRITE;
g_dmaCTRLPKT2.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT2.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT2.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT2.ADDMODERD = ADDR_OFFSET; /* address mode read */
g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT2.AUTOINIT = AUTOINIT_ON; /* autoinit */
/* upto 32 control packets are supported. */
/* - setting dma control packets */
dmaSetCtrlPacket(DMA_CH2,g_dmaCTRLPKT2);
dmaSetCtrlPacket(DMA_CH3,g_dmaCTRLPKT1);
/* - setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH2, DMA_HW);
dmaSetChEnable(DMA_CH3, DMA_HW);
dmaReqAssign(DMA_CH0, DMA_REQ0); //TG0 RX
dmaReqAssign(DMA_CH1, DMA_REQ1); //TG0 TX
dmaReqAssign(DMA_CH2, DMA_REQ5); //TG1 RX
dmaReqAssign(DMA_CH3, DMA_REQ4); //TG1 TX
/* - configuring the mibspi dma , channel 0 , tx line - 0 , rxline - 1 */
/* - refer to the device data sheet dma request source for mibspi tx/rx */
mibspiDmaConfig(mibspiREG1,0,0,1);
/* - configuring the mibspi dma , channel 1 , tx line - 3 , rxline - 2 */
mibspiDmaConfig(mibspiREG1,1,3,2);
dmaEnable();
/* - start the mibspi transfer tg 0 and tg 1 */
mibspiTransfer(mibspiREG1, 0);
mibspiTransfer(mibspiREG1, 1);
while(1); /* loop forever */
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
/** void mibspiEnableLoopback(mibspiBASE_t *mibspi )
*
* enabling internal loopback on mibspix
*/
void mibspiEnableInternalLoopback(mibspiBASE_t *mibspi )
{
/* enabling internal loopback */
mibspi->GCR1 |= 1U << 16U;
}
/** void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)
*
* configuring mibspi dma with
*
* channel > mibspi dma channel number
* txchannel > transmit channel dedicated for mibspi
* rxchannel > receive channel dedicated for mibspi
*/
void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)
{
uint32 bufid = D_SIZE - 1;
uint32 icount = 0;
/* setting transmit and receive channels */
mibspi->DMACTRL[channel] |= (((rxchannel<<4)|txchannel) << 16);
/* enabling transmit and receive dma */
mibspi->DMACTRL[channel] |= 0x8000C000;
/* setting Initial Count of DMA transfers and the buffer utilized for DMA transfer */
mibspi->DMACTRL[channel] |= (icount << 8) |(bufid<<24);
}
/** void loadDataPattern(uint32 psize, uint16* pptr)
*
* loading a randam data chunk into system ram
*
* pptr > sys ram address
* psize > chunkl size
*
*/
void loadDataPattern(uint32 psize, uint16 * pptr)
{
int i;
for(i = 0; i < psize; i++)
{
TG0_TXDATA[i] = i;
TG1_TXDATA[i] = i+64;
}
}
/* USER CODE END */
