TMS570LC4357-EP: Regarding Interconnect Self-test

Hi,

 Did you follow the below sequence?

Can you show your code sequence?

Did you observe the CPU reset?

Did you see any flags set in SDC_STATUS register? See below. Please also be aware of errata DEVICE#51 that the status will be left-shifted by 24 bits. 

Can you show the ESM log?

Hi Charles-san,

Thank you for your reply.

Interconnect self-test is successful, and we would like to verify notification of ESM3.12,.

My code sequence is below(using Hercules SafeTI Diagnostic Library V.2.4.0);

1) SL_SelfTest_MemoryInterconnect(MEMINTRCNT_SELFTEST)

2) CPU Reset

3) SL_SelfTest_Status_MemIntrcntSelftest()

Each status register of ESM and SDC is no error.

・ESM
ESMSR1: 0x00000000
ESMSR2: 0x00000000
ESMSR3: 0x00000000
ESMSR4: 0x00000000
ESMSR7: 0x00000000
・SDC
SDC_STATUS: 0x0A000000 - NT_OK(3) & PT_OK(1)

Could you please tell me about technique of generating ESM3.12?
Please advice.

Thanks,

Sho

Kobori-san,

  I think ESM3.12 is only asserted if the selftest fails. Since the selftest does not fail, no error signal is asserted to ESM module. You should read the PT_OK and NT_OK bits. If they are set, it means the selftest is done without errors. 

4.3.4 Interconnect Self-test
CPU Interconnect Subsystem can be put into self-test. When in self-test, the self-test logic will apply test
stimulus to each master and slave interface. If an error is detected, the type of error for the corresponding
interface is logged. An error is asserted to ESM Group 3 if the self-test does not complete successfully.
NOTE: Application must only launch CPU Interconnect Subsystem self-test when there are no bus
transactions from any masters including the CPU cores. While in self-test, the interconnect
can not service any requests. Bus master requests can be lost or corrupted. It is recommend
that the self-test is only exercised as part of the device initialization before any master is
setup by the CPU.
To launch the self-test, the applicable must follow the below sequence:
1. Write 0xA key to the DTC_ERROR_RESET bits of the SCMCNTRL register in the SCM module.
2. CPU executes WFI instruction to put itself in idle state. The start of self-test is gated by the idle state of
the CPU.
3. When both step 1 and 2 are met, the self-test will start. While self-test is on-going, the CPU cores is
forced into reset. Note that reset is only held to the CPU cores while the rest of the system is not.
4. When self-test is complete, the DTC_ERROR_RESET bits is automatically reverted back to 0x5 as the
reset value.
5. After the self-test is complete, a reset is applied to the CPU Interconnect Subsystem for 16 HCLK
cycles. During this time, the CPU is also held in reset.
6. After the interconnect and the CPU comes out of the reset, normal code execution can then start. CPU
can check the self-test status by reading the NT_OK bit and the PT_OK bit of the SDC_STATUS
register. These two bits indicate if the negative test and positive self-test sequence have passed. In
addition, if the self-test has failed, the error is asserted to the ESM module.

Hi Charles-san,

Thank you for your information.

I understood ESM 3.12 should be occurred when Interconnect self-test failed.
However, my test code invariably success interconnect self-test.

I would like to verify notification of ESM 3.12, could you please tell me about forcibly technique of failing Interconnect self-test?

Thanks,

Sho

Hi Charles-san,

Thank you for your support.

Best regards,

Sho