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TMS570LC4357-EP: Regarding Address Parity Override of L2RAMW

Sho Kobori
Intellectual 640 points
Part Number: TMS570LC4357-EP


Hello, 

This is a question about ESM3.15 and Address Parity Override of L2RAMW.


To verify notification of ESM3.15, We created the following test code based on Sec 8.3.1 of SPNU563A.

test code:
volatile uint32 *ramtest = 0x08000000;
volatile uint32 bakRAMCTRL;
volatile uint32 tmp;
*ramtest = 0x12345678;
bakRAMCTRL = l2ramwREG->RAMCTRL;
l2ramwREG->RAMCTRL = (bakRAMCTRL & 0xF0FFFFFFU) | (0xAU << 24);
tmp = *ramtest;
l2ramwREG->RAMCTRL = bakRAMCTRL;

Each status register:
・ESM
ESMSR1: 0x00000000
ESMSR2: 0x00000080 (ESM 2.7)
ESMSR3: 0x00008000 (ESM 3.15)
ESMSR4: 0x00000000
ESMSR7: 0x00000000
・L2RAMW
RAMERRSTATUS: 0x00008100 - CPEOI(15) & PACE(8)


ESM3.15 and ESM2.7 was generated when this test code executed.
Is this operation of MCU correct?(Why is ESM2.7 generated?)

Thanks,

Sho.

  • 0
    TI__Guru**** 191906 points
    Sho Kobori said:
    ESM3.15 and ESM2.7 was generated when this test code executed.
    Is this operation of MCU correct?(Why is ESM2.7 generated?)

    Hi,

      I don't see a problem with your code sequence.  I think while doing the diagnostic for ESM2.7, an parity error on the command byte is also detected resulting in ESM2.7.

  • 0 in reply to Charles Tsai
    Intellectual 640 points

    Hi Charles-san,

    Thank you for your support, We have a additional question about CPEOI(15) of RAMERRSTATUS in L2RAMW.

    Regarding IDLE command of L2RAMW, Is there documents explained detail information? please advice me.

    Thanks,

    Sho

  • +1 in reply to Sho Kobori
    TI__Guru**** 191906 points

    Hi Kobori-san,

      I'm not sure if we are getting into to too much details here. The L2RAMW is an RAM wrapper controller module with OCP bus interface. Please refer to https://www.accellera.org/downloads/standards/ocp/files on the OCP specification. In this bus protocol, there is a MCmd signal with the below encoding. Master such as CPU will carry this signal after conversion. The reason I say after conversion is because Cortex-R5 has a native AXI bus interface. There is a conversion from AXI to OCP first. MCmd signal indicates to the slave (e.g. L2RAMW) what type of transaction the master wants to carry. When the master is not sending any command to the slave, it will indicate with IDLE. When you put L2RAMW in the forced parity error test, it also detect a parity error on the bus while the bus is in IDLE. I hope I'm not giving too much design details. 

  • 0 in reply to Charles Tsai
    Intellectual 640 points

    Hello Charles-san,

    Thank you for your support.

    Regards,

    Sho