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TMS570LC4357: 32 bit writes to FPGA device through EMIF resulting in 64bit writes

chaitanya kumar B
Prodigy 70 points
Part Number: TMS570LC4357

Hi team, we are interfacing an FPGA with EMIF interface and is using CS0. The Asyinc1 is configured with 0x04E22715 value. We are trying to write 32bits of data into FPGA memory but we are noticing that the data which is getting written is 64bits through EMIF. We are not quite sure what could be an issue here. My understanding is the 32bits of data gets written to the specified address in chunks of two 16bits in one Chip select time frame. However it is appearing that the data is getting written is 64bits. Can you please let us know what could be a potential issue for this?

  • 0
    TI__Guru**** 196116 points

    Hi Chattanya,

    The EMIF module supports 16-bit SDRAM in addition to the asynchronous memories. It has a single SDRAM chip select (EMIF_nCS[0]), and three chip selects (EMIF_nCS[4:2]) for asynchronous memories.

    If the FPGA is configured as async memory, it's CS should be connected to EMIF CS[2] or CS[4:3].

  • 0 in reply to QJ Wang
    Prodigy 70 points

    Hi Wang, it is my bad, the CS is actually being used is CS2 and not CS0. 

    The PMCR value is 0xFCFCFC04, CE2CFG is configured with 0x04E22715 and bits 29 (WP1) and (WP0) 28 of AWCCR are set to 1 respectively.

    do you have any recommendations on any other settings that we might be missing?

  • 0 in reply to chaitanya kumar B
    TI__Guru**** 196116 points

    I don't know what causes this issue.

    If you declare a addr as int (for example unsigned int *Addr ;), a 32-bit word will be written.

    If you declare a addr as long (for example unsigned long long int * Addr;), a 64-bit word will be written.

  • 0 in reply to QJ Wang
    Prodigy 70 points

    Hi Wang, Its not about the variable declaration, we are trying to write directly to the memory using memory window at the address of FPGA, even then we are seeing the same behavior. 

  • 0 in reply to chaitanya kumar B
    TI__Guru**** 196116 points

    An asynchronous request for 4 bytes will require only two access cycle using a 16-bit data bus. It should not write another 4 bytes. Does 2nd word written to FPGA same as the first word? Can you write code to read the 64-bit data back after writing the 32-bit data?

    How is the FPGA connected to EMIF? For 16-bit async memory, the EMIF_BA[1]  pin provide the least-significant bits of the halfword, so BA[1] should be connected FPGA_ADDR[0], and EMIF_ADDR[0] is connected to FPGA_ADDR[1]