Hello,
This is a question regarding forcibly generating ESM1.26.
We are now testing the ESM function of TMS570 MCU on the evaluation board.
From contents of described Sec 8.2.2.4 of SPNU563A, We think CPUWE(0) of RAMERRSTATUS register in L2RAMW is one of error source in order to generate ESM1.26.
To verify notification of ESM1.26, Could you please tell me about technique of forcibly generating ESM1.26?
Thanks,
Sho
Hi Kobori-san,
CPUWE bit is set when CPU writes to L2RAMW and cause L2RAMW to detect a single bit ECC error. Let me briefly explain a CPU write transaction. When CPU (e.g. Cortex-R5F core) writes to L2RAMW, it will drive the 64-bit data on its WDATAMm[63:0] bus. It will also drive the ECC code for the corresponding data on WERRCODEMm[7:0] bus. Please find the below signals. If you want to read the detail of the entire Cortex-R5 AXI interface signals, please refer to Cortex-R5 TRM at https://developer.arm.com/documentation/ddi0460/d.
When L2RAMW receives the write request from the master, it will calculate its own ECC for the data on WDATAMm bus. The calculated ECC is then checked against the received ECC on WERRCODEMm. This is basically how ECC checking works and I think this is clear to you.
Now the question from you is how to 'force' an ECC correctable error so CPUWE bit and ESM 1.26 will set. This is actually not possible because this is a runtime diagnostic check on CPU. The only time CPUWE and ESM 1.26 will set is when the calculated ECC by L2RAMW is different from WERRCODEMn. There is no mechanism in Cortex-R5 to force a bit flip on either WDATAMn or WERRCODEMn bus on a simple bench setup.
If you run Diagnostic test outlined in 8.2.6 then DWSE flag which is bit 19 of RAMERRSTATUS register can set if it fails the single bit error diagnostic for write transactions.
