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I understand MPU1_0 (a53 core) Linux can control the PCIe EP(End Point).
But I want to use MCU1_0 (r5f core) on AM64x for this purpose.
... AM64x AM243x TRM(Technical Reference Manual), spruim2c.pdf ...
2.1 Main Domain Memory Map
----> found names 'PCIE0_CORE_ECC_AGGR0', 'PCIE0_CORE_DBN_CFG_PCIE_CORE', 'PCIE0_DAT0', ...
2.2 MCU Domain Memory Map
----> not found name concerned with PCIe...
Can MCU1_0 (r5f core) access the PCIe control registers directly?
Hi,
I'm not TI, so you might want to wait for an official reply, but here's what I know:
- the MCU1_0 (actually all the R5f cores) in the AM64x are in the main domain. The MCU domain is only the M4 core.
- Yes, MCU1_0 can access the PCIe controller registers
- As far as I know there is no software support from TI (yet). Someone from TI might know more about that.
Regards,
Dominic
Thanks, I understood R5f cores are in the main domain.
I will close this thread.
Regards, :-)
Hi Dominic,
Thanks for your kind reply.
All your replies are correct. MCU1_o can access PCIE. As you said we don't support PCIE in our SDK yet.
Regards,
Prasad