Phenomenon:
Data is inverted: the transmit data is 1, 2, 3, 4, 5 6,7,8, the actual data received is: 2,1, 4, 3, 6, 5, 8 7.
The codes are as follows:
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "sys_common.h"
/* USER CODE BEGIN (1) */
#include "sys_vim.h"
#include "esm.h"
#include "can.h"
#include "dcc.h"
#include "sys_core.h"
#include "spi.h"
#include "system.h"
#include "rti.h"
#include "data.h"
#include "sys_dma.h"
#include <stdio.h>
#include <string.h>
/* USER CODE END */
/** @fn void main(void)
* @brief Application main function
* @note This function is empty by default.
*
* This function is called after startup.
* The user can use this function to implement the application.
*/
/* USER CODE BEGIN (2) */
#define D_SIZE2 9
uint8 Tx_data[D_SIZE2] = { 'H', 'E', 'R', 'C', 'U', 'L', 'E', 'S', '\0' };
uint8 Tx1_data[D_SIZE2] = { 'S', 'F', 'F', 'E', 'R', 'A', 'G', 'V', '\0' };
uint8 Rx_data[D_SIZE2] = { 0 };
uint8 num;
uint32 ID_data[8];
/*uint32 error = 0;*/
/*SPI data define*/
uint16 TG0_TX_DATA[8] = { 0x1000, 0x1111, 0x1222, 0x1333, 0x1444, 0x1555,
0x1666, 0x1777 };
uint16 TG0_RX_DATA[8] = { 0 };
uint16 TG1_TX_DATA[8] = { 0x2000, 0x2111, 0x2222, 0x2333, 0x2444, 0x2555,
0x2666, 0x2777 };
uint16 TG1_RX_DATA[8] = { 0 };
uint16 TG2_TX_DATA[8] = { 0x3000, 0x3111, 0x3222, 0x3333, 0x3444, 0x3555,
0x3666, 0x3777 };
uint16 TG2_RX_DATA[8] = { 0 };
uint16 TG3_TX_DATA[8] = { 0x4000, 0x4111, 0x4222, 0x4333, 0x4444, 0x4555,
0x4666, 0x4777 };
uint16 TG3_RX_DATA[8] = { 0 };
uint32_t TG3_IS_Complete;
uint32 checkPackets(uint8 *src_packet, uint8 *dst_packet, uint32 psize);
#define D_COUNT 8
uint32 cnt = 0, error = 0, tx_done = 0;
uint8 tx_data[D_COUNT][8] = { 0 };
uint8 rx_data[D_COUNT][8] = { 0 };
uint8 tx1_data[D_COUNT][8] = { 0 };
uint8 rx1_data[D_COUNT][8] = { 0 };
uint8 *tx_ptr = &tx_data[0][0];
uint8 *rx_ptr = &rx_data[0][0];
uint8 *tx1_ptr = &tx1_data[0][0];
uint8 *rx1_ptr = &rx1_data[0][0];
uint8 *dptr = 0;
void dumpSomeData();
#define D1_SIZE 127
void loadDataPattern(uint32 psize, uint16* pptr);
void dmaConfigCtrlRxPacket(uint32 sadd, uint32 dadd, uint16 dsize, uint16 BlockSize);
void dmaConfigCtrlTxPacket(uint32 sadd, uint32 dadd, uint16 dsize, uint16 BlockSize);
unsigned int SPI_TestVerify();
/* example data Pattern configuration */
//#define SPI1_RXBUF 0xFFF7F442
//#define SPI3_TXBUF 0xFFF7F83E
#define SPI4_TX_ADDR ((uint32_t)(&(spiREG4->DAT1)) + 2)
#define SPI4_RX_ADDR ((uint32_t)(&(spiREG4->BUF)) + 2)
unsigned int BlockSize = 100;
unsigned short TX_DATA[100];
uint8 tx_test[8]={1,2,3,4,5,6,7,8};
uint8 rx_test[8]={0};
unsigned short RX_DATA[100] = {0};
unsigned int SPI4_HBCFlag = 0;
unsigned int SPI4_BTCFlag = 0;
unsigned int txrx_error;
g_dmaCTRL g_dmaCTRLPKT_TX, g_dmaCTRLPKT_RX; /* dma control packet configuration stack */
/* USER CODE END */
int main(void)
{
/* USER CODE BEGIN (3) */
int i=0;
spiDAT1_t dataconfig1_t;
dataconfig1_t.CS_HOLD = FALSE;
dataconfig1_t.WDEL = TRUE;
dataconfig1_t.DFSEL = SPI_FMT_0;
dataconfig1_t.CSNR = 0xFE;
TG3_IS_Complete = 0x55555555;
_enable_interrupt_();
_enable_IRQ();
rtiInit();
canInit();
dccInit();
spiInit();
rtiEnableNotification(rtiNOTIFICATION_COMPARE0);
rtiStartCounter(rtiCOUNTER_BLOCK0);
canEnableloopback(canREG1, Internal_Lbk);
canEnableErrorNotification(canREG1);
canEnableErrorNotification(canREG2);
spiEnableNotification(spiREG4, 1);
spiSendAndGetData(spiREG4, &dataconfig1_t, 16, TG0_TX_DATA, TG0_RX_DATA);
/********DMA***********************/
do
{
/* - enabling dma module */
dmaEnable();
/* Enable Interrupt after reception of data */
dmaEnableInterrupt(DMA_CH0, FTC); //Frame transfer complete
/* - assigning dma request: channel-0 with request line - 0/15 */
dmaReqAssign(DMA_CH1, 24); //Request line 24:SPI4 RX
dmaReqAssign(DMA_CH2, 25); //Request line 25:SPI4 TX
/* - configuring dma TX control packets */
dmaConfigCtrlTxPacket(tx_test, SPI4_TX_ADDR, 1, 4);
dmaSetCtrlPacket(DMA_CH2, g_dmaCTRLPKT_TX);
dmaConfigCtrlRxPacket(SPI4_RX_ADDR,rx_test, 1, 4);
dmaSetCtrlPacket(DMA_CH1, g_dmaCTRLPKT_RX);
/* - setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH1, DMA_HW); //SPI1 RX, hardware triggering
dmaSetChEnable(DMA_CH2, DMA_HW); //SPI3 TX, hardware triggering
spiREG4->GCR1 = (spiREG4->GCR1 & 0xFFFFFFFFU) | (0x1 << 24); //Enable SPI
spiREG4->INT0 = (0x1 << 16); //SPI_DMAREQ; Enable DMA REQ only after setting the SPIEN bit to 1.
/*while( SPI4_BTCFlag == 0 )
{ //DMA block complete interrupt
}
if (SPI4_BTCFlag == 1)
{
spiREG4->PC3 = 0x01; //CS[0]=1
txrx_error = SPI_TestVerify(); //to check if rxed data is same as the txed data
}*/
}
while (txrx_error>0);
while (1)
{
}
/* USER CODE END */
return 0;
}
/* USER CODE BEGIN (4) */
void canMessageNotification(canBASE_t *node, uint32 messageBox)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (15) */
if (node == canREG1)
{
tx_done = 1; /* confirm transfer request */
while (!canIsRxMessageArrived(canREG1, canMESSAGE_BOX2))
;
canGetData(canREG1, canMESSAGE_BOX5, Rx_data); /* copy to RAM */
canTransmit(canREG1, canMESSAGE_BOX1, Rx_data);
//rx1_ptr +=8;
}
/* node 2 - receive complete */
if (node == canREG2)
{
while (!canIsRxMessageArrived(canREG2, canMESSAGE_BOX1))
;
canGetData(canREG2, canMESSAGE_BOX1, rx_ptr); /* copy to RAM */
ID_data[num] = canGetID(canREG2, canMESSAGE_BOX1);
num++;
if (num > 8)
num = 0;
rx_ptr += 8;
}
}
void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
{
if (inttype == HBC) {
SPI4_HBCFlag = 1;
}
else if (inttype == BTC){
SPI4_BTCFlag = 1;
}
}
//DMA receive data initialization
void dmaConfigCtrlRxPacket(uint32 sadd, uint32 dadd, uint16 ElmntCnt, uint16 FrameCnt)
{
g_dmaCTRLPKT_RX.SADD = sadd; /* source address */
g_dmaCTRLPKT_RX.DADD = dadd; /* destination address */
g_dmaCTRLPKT_RX.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT_RX.FRCNT = FrameCnt; /* frame count */
g_dmaCTRLPKT_RX.ELCNT = ElmntCnt; /* element count */
g_dmaCTRLPKT_RX.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_RX.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_RX.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_RX.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_RX.PORTASGN = 4; /* port b */
g_dmaCTRLPKT_RX.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT_RX.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT_RX.TTYPE = FRAME_TRANSFER; /* transfer type */
g_dmaCTRLPKT_RX.ADDMODERD = ADDR_FIXED; /* address mode read */
g_dmaCTRLPKT_RX.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT_RX.AUTOINIT = AUTOINIT_ON; /* autoinit */
}
//DMA transmit data initialization
void dmaConfigCtrlTxPacket(uint32 sadd, uint32 dadd, uint16 ElmntCnt, uint16 FrameCnt)
{
g_dmaCTRLPKT_TX.SADD = sadd; /* source address */
g_dmaCTRLPKT_TX.DADD = dadd; /* destination address */
g_dmaCTRLPKT_TX.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT_TX.FRCNT = FrameCnt; /* frame count */
g_dmaCTRLPKT_TX.ELCNT = ElmntCnt; /* element count */
g_dmaCTRLPKT_TX.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_TX.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_TX.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_TX.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_TX.PORTASGN = 4; /* port b */
g_dmaCTRLPKT_TX.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT_TX.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT_TX.TTYPE = FRAME_TRANSFER; /* transfer type */
g_dmaCTRLPKT_TX.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT_TX.ADDMODEWR = ADDR_FIXED; /* address mode write */
g_dmaCTRLPKT_TX.AUTOINIT = AUTOINIT_ON; /* autoinit */
}
void loadDataPattern(uint32 psize, uint16* pptr)
{
*pptr = 0x0;
while(psize--)
{
// *pptr = 0x1111 + *pptr++;
*pptr++ = psize + 0x5A00;
}
}
unsigned int SPI_TestVerify()
{
register unsigned short i;
register unsigned int error;
register unsigned short * dst_address;
//Checking the received data with transmitted data
error = 0;
if(SPI4_HBCFlag > 0)
{
dst_address = RX_DATA;
for(i=0;i<50; i++) {
if( *dst_address++ != TX_DATA[i])
{
error ++;
}
}
}
else
{
dst_address = &RX_DATA[50];
for(i=50; i<100; i++) {
if( *dst_address++ != TX_DATA[i])
{
error ++;
}
}
}
return error;
}
/* USER CODE END */
Could you please help check it?
Thanks!
Best Regards,
Cherry Zhou
