• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 2 answers
  • Subscribers 31 subscribers
  • Views 708 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137: Unaligned access to SDRAM

Christian Fuchs1
Expert 1250 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hello.

I've attached a SDRAM over EMIF.

Now I've tried some memory configurations and if unaligned writes to the SDRAM are working (always with enabled MPU):

For "strongly order" and "device" configuration an unaligned write is not possible.

For "cacheable bufferable" an unaligend write is possible.

Also if MPU is disabled the unaligned write is not possible.

But which memory configuration is the right one?

Thanks and BR

Christian

  • 0
    TI__Guru**** 196306 points

    Hi Christian,

    The TMS570LS3137 device doesn't have cache. Cacheable doesn't apply to this device. 

    You can use Normal mode. 

  • 0 in reply to QJ Wang
    Expert 1250 points

    Hi QJ.

    What will happen if I use cacheable? Because then an unaligned write works. (and thats great for packed structs)

    Thank you

    BR

    Christian

  • 0 in reply to Christian Fuchs1
    TI__Guru**** 196306 points

    The unaligned accesses to Strongly-ordered or Device memory is not permitted. 

  • 0 in reply to QJ Wang
    Expert 1250 points

    Yes, I know. But what happens if I configure the memory as "cacheable bufferable"? Because then, unaligned access works!

  • 0 in reply to Christian Fuchs1
    Guru 92251 points
    Christian Fuchs1 said:
    What will happen if I use cacheable? Because then an unaligned write works.

    From reading the ARM documentation it is clear that only the Normal Memory type attribute supports unaligned accesses.

    Memory system implications for AXI accesses in the Cortex-R4 and Cortex-R4F Technical Reference Manual contains:

    However, Device and Strongly-ordered memory is always Non-cacheable. Also, any unaligned access to Device or Strongly-ordered memory generates an alignment fault and therefore does not cause any AXI transfer. This means that the access examples given in this chapter never show unaligned accesses to Device or Strongly-ordered memory.

    Section A3.5.4 Normal memory in ARM v7-M Architecture Reference Manual (ARM DDI 0403E.d) contains:

    Normal memory is idempotent, meaning that it exhibits the following properties:
    • Unaligned accesses can be supported.

    Since the TMS570LS3137 doesn't have a cache think the MPU Region Access Control for the EMIF needs to configure the TEX[2:0], C, and B encodings as "Outer and Inner Non-cacheable" and "Normal" as per the following from the Cortex-R4 and Cortex-R4F Technical Reference Manual:

    I haven't (yet) traced the above setting to the HALCoGen GUI configuration options.

  • 0 in reply to Chester Gillon
    Expert 1250 points

    Hi Chester.

    Thank you for the detailed answer.

    Does this also applie to internal RAM?

  • 0 in reply to Christian Fuchs1
    Guru 92251 points
    Christian Fuchs1 said:
    Does this also applie to internal RAM?

    Given that access to internal RAM and SDRAM over EMIF are both idempotent in terms of the ARM definition of Normal memory then yes.

  • +1 in reply to Chester Gillon
    Guru 92251 points
    Chester Gillon said:
    I haven't (yet) traced the above setting to the HALCoGen GUI configuration options.

    I had a look at a HALCoGen project created for a RM48L952ZWT (a Cortex-R4F based device with an EMIF).

    In the default MPU settings created at project initialisation:

    a. MPU Region 3 which covered the internal RAM had a type of "NORMAL_OINC_NONSHARED" (Memory type normal outer and inner non-cachable and non-shared) in the HALCoGen R4-MPU-MPU tab.

    b. MPU Region 6 which covered the EMIF SDRAM had a type of "STRONGLY_ORDERED_SHAREABLE" (Memory type strongly ordered and shareable) in the HALGoGen R4-MPU-MPU tab.

    Looking at the sys_mpu.asm to look at the MPU Region Access Control Register settings used, and based the information in the Cortex-R4F TRM:

    Type in HALCoGen MPU configuration MPU Region Access Control Register value (as set by sys_mpu.asm) TEX S C B Description Memory Type Shareable?
    NORMAL_OINC_NONSHARED 0x0308 b001 0 0 0 Outer and Inner Non-cacheable Normal  Non-shared
    STRONGLY_ORDERED_SHAREABLE 0x0300 b000 0 0 0 Strongly-ordered Strongly-ordered Shared

    Based upon the above, if you want to use the EMIF SDRAM region to allow unaligned accesses then a type of NORMAL_OINC_NONSHARED should be selected in the HALCoGen MPU configuration.