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TMS570LS1227: when CPU and RAM self-test, how to perform fault injection, and how to view the self-test results

Part Number: TMS570LS1227
Other Parts Discussed in Thread: HALCOGEN

Hi team,

CPU and RAM self-test using STC and PBIST, HCG options are shown in the figure below:

1. what does each option mean, after checking, the CPU self-test needs to pass the LBIST, but there is no corresponding option in HCG.

2. how to inject a self-test fault, including a CPU fault and a RAM fault.

3. according to the manual, it is not possible to run the self-test in debug mode, so how can the customer see the fault information of the failed self-test?

Could you help to resolve this case?

Thanks!

Best Regards,

Cherry

  • Hi Cherry,

    HALCoGen was developed before SafeTI diagnostics library hence there are few overlapping Safety Diagnostics features between them. We continue to support HALCoGen diagnostics ( sys_selftest.c) for legacy reasons. We strongly recommend to use SafeTI Diagnostics library (SDL) for Safety Functions.

    Please refer to the user guide of SDL:

    C:\ti\Hercules\SafeTI Diagnostic Library\2.4.0\docs\SafeTIDiagnosticLibrary-User'sGuide-v2.4.0.htm

  • 1. what does each option mean, after checking, the CPU self-test needs to pass the LBIST, but there is no corresponding option in HCG.

    Aall the functions generated are located in sys_selftest.c.

    The 1st panel is to generate selftest code. 

        Enable CCM Self test: ccmSelfCheck();

        Enable CPU self test: stcSelfCheck();
                                           cpuSelfTest(...)

        EFuse self test: efcCheck();
                                  efcSelfTest();

        Enable PBIST Self Test:  pbistSelfCheck();


        Enable FMCBUS2 Error check: fmcBus2Check();

        Enable Flash ECC check:  checkFlashECC();

        Enable SRAM ECC check:  checkB0RAMECC();  checkB1RAMECC();

    The 2nd panel is for PBIST:

    pbistrun()

    The 3nd panel is for parity check:

    void vimParityCheck(void);
    void dmaParityCheck(void);
    void adc1ParityCheck(void);
    void adc2ParityCheck(void);
    void het1ParityCheck(void);
    void htu1ParityCheck(void);
    void het2ParityCheck(void);
    void htu2ParityCheck(void);
    void can1ParityCheck(void);
    void can2ParityCheck(void);
    void can3ParityCheck(void);
    void mibspi1ParityCheck(void);
    void mibspi3ParityCheck(void);
    void mibspi5ParityCheck(void);

    void enableParity(void);
    void disableParity(void);

  • 2. how to inject a self-test fault, including a CPU fault and a RAM fault.

    Please take a look at the following function: 

    ccmSelfCheck();

    and

    checkB0RAMECC();  

    checkB1RAMECC();

    3. according to the manual, it is not possible to run the self-test in debug mode, so how can the customer see the fault information of the failed self-test?

    You can not run CCM selftest in debug-mode. You can perform other selftest (STC, CPU, PBIST, etc) in debug mode.

  • Hi Wang,

    Thank you so much!

    And the customer also would like to know if the self-test fault injection only be done by modifying CCMUYR = 0x9U in functions such as ccmSelfCheck.

    May I know is there any other way to inject the self-test fault of the CPU and RAM outside of the chip without modifying the code? 

    Thanks!

    Best Regards,

    Cherry

  • Hi Cherry,

    Yes, MKEY=0x9 is to inject fault or error forcing.

    Error forcing mode is similar to the compare mismatch test operation of self-test mode.

    May I know is there any other way to inject the self-test fault of the CPU and RAM outside of the chip without modifying the code? 

    No.