SPI receive complete to triggered DMA transfer large delay

Hi Tony,

I'm consulting on this point with our design team.

By the way in case 1 what timings you would get if you call the DIO pin toggle routine once the SPI receive falg is set (instead of the DMA frame complete interrupt).

Best Regards,

Pratip

Hi Pratip,

I'm not quite sure what you're asking for. My case 2 illustrates what the time from end of SPI receive (i.e. receive complete) straight to ISR would be. I would expect the DMA in case 1 to be started in much the same time as the SPI interrupt in case 2, i.e. one or two microseconds. I think the DMA operation itself takes something in the order of 1us, it is only transferring some 8 16-bit words.

Regards, Tony.

Hi Pratip,

An additional experiment I've just tried. If I activate the DMA transfer by software from the SPI receive interrupt of case 2, then the DMA frame transfer complete occurs within 2.5us from the SPI receive interrupt.

   ________
  |        |
__|        |_______________________________________________ SPI CS
           .
           .            ____
           .           |    |
_______________________|    |______________________________ SPI Receive Complete ISR
           .           .    .
           .<- t_spi ->.    .
                            .                   ____
                            .                  |    |
_______________________________________________|    |______ DMA Frame Transfer Complete ISR
                            .                  .
                            .<---- t_dma ----->.

t_spi = 1.2us
t_dma = 2.5us

Regards, Tony.

Tony,

Okay. So you are transfering a very few data packets. I see the point.

Infact the call to the interrupt and the DMA both happen at the same time. So ideally no delay is expected in starting the DMA for sure.

The only area that we can doubt is, if the DMA is loaded with any other operation at higher priority than this SPI receive data transfer that keeps the DMA controller busy.

Best Regards,

Pratip

Hi Pratip,

Unfortunately, this is the only DMA I have configured and running, so DMA busy is not the explanation. And from my example, you can see that DMA software activated from SPI receive complete ISR is not delayed, whilst DMA hardware activated directly from SPI receive complete is delayed.

Is there any requirement for me to configure the DMA settings available within the SPI module which would impact on its priority?

Regards, Tony.

Hi,

I wonder if anybody at TI can perform a quick evaluation to see if my problem is reproducible. I would really like to find a better solution that my current one (generate an FIQ which itself starts the DMA).

Regards, Tony.

Hi,

Would you be able to provide the SPI and DMA settings code to have a look ?

Regards,

Pratip

Hi Pratip,

This code is embedded within a larger project which is subject to NDA. I would rather, however, that TI were able to try and reproduce this with a much simpler project to see whether it is most likely something to do with my particular project, or hether it is a more fundemental problem with the TMS570. If TI would rather I try with a simple project then I can, I just thought you would have many simple example projects which could be easily modified.

Let me know if you would like me to try a simpler project here first.

Regards, Tony.

Tony,

I was just looking for a code snippet or register settings of DMA and SPI .

Let me try and extraxt a code snippet of the SPI DMA settings from my side meanwhile.

Regards,

Pratip

Hi Tony,

1) When you are using SPI RX DMA hope you have not enabled any SPI receive buffer Full Interrupt. 
2) Can you pls send us the DMA control packet configuration( i.e FRAME TRANSFER, SIZE info, SOURCE, AUTOINIT on/off etc) used.

Best Regards
Prathap

Hi Pratip,

1) I don't have SPI RXBUF FULL interrupt enabled when trying to get SPI RX DMA working.

2) My DMA settings are:

(regSpi[SPI_MODULE_1_E]).DMAxCTRL[0] = 0x00008000;  /* SPI DMA Channel Control Register (DMAxCTRL)
                                                    0000 0000 0000 0000 1000 0000 -000 0000
                                                    0                                       ONESHOT
                                                     000 0000                               BUFIDx
                                                              0000                          RXDMA_MAPx
                                                                   0000                     TXDMA_MAPx
                                                                        1                   RXDMAENAx
                                                                         0                  TXDMAENAx
                                                                          0                 NOBRKx
                                                                           0 0000           ICOUNTx
                                                                                   0        COUNTBIT17x
                                                                                    00 0000 COUNTx */

Hi Tony,

Looking at the code I think you are using DMA with MIBSPI mode not SPI Mode( Compatibility Mode)... i.e.. MibSPI ENA bit in MIBSPIE register(offset 0x70) in the module is set to 1, Am I right? My earlier comment was under assumption that you are using the module in Compatibility Mode( Just SPI)  

Are you trying to receive 9 - 16bit data and generate DMA request to transfer it to System RAM? or for every 16bit data received you want DMA to transfer? I see you have configured as Frame transfer with Element count as 9, so FRAME complete interrupt will occur only after 9 16 bit datas are transfered.

If you want to transfer 9 - 16 Bit valid SPI data then try using MIBSPI buffer 9 (using BUFID in (regSpi[SPI_MODULE_1_E]).DMAxCTRL[0])  to trigger DMA request, so that after receiving all 9 16bit SPI data in the RX RAM a DMA trigger will occur and will transfer data from Buffer 0 (since in DMA control packet source is RXRAM 0) to 9 to the destination system RAM. Using AUTOINIT and frame offset if required,  you can use the same configuration to receive multiple frames.

Why are you using DMA channel chaining? Is it for other purpose or same SPI transfer? Just trying to understand.

If I get the exact useage I can help you with better solution.

I am adding you as my friend to support if something specific you want to share.

Best Regards
Prathap

Hi Prathap,

You're right, I'm not using SPI Compatibility mode. the MIBSPI provides some useful benefits I think that I wouldn't otherwise get (particularly memory fault protection and DMA interface).

My scenario is described in other forum post Re: Complex SPI, DMA, CRC, RTI, FIQ integration scenario. Basically, I am receiving a 9*16-bit transfer which must be transferred from RXRAM to to my own circular RAM buffer; this must then CRC'd before being made available to my application as valid, and its exact time of receipt must be recorded. I must also prepare the responding transmit data which must be copied to SPI TXRAM from an internal RAM buffer, and a CRC added. I'll send you diagram of my Master and Slave requirements (termed Primary and Secondary here) for your interest.

You will see from yet another forum post that I am having trouble with data receipt, Re: SPI Receive RXRAM all-zero without XDS510 connected. Sunil is helping me with this, but if you have any ideas!

Regards, Tony.