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TMS570LC4357-EP: NOINIT RAM section

Domenico Margiotta
Prodigy 40 points
Part Number: TMS570LC4357-EP
Other Parts Discussed in Thread: TMS570LS3137, , TMS570LC4357, HALCOGEN

Hello everyone,

in my project I would like to store some variable values in RAM in order to read back it again after a reset caused by an external watchdog reset.

To do it, I have created a dedicated section in section configuration and in the memory map I have reserved a portion of RAM as RAMNONINIT. This approach it is successfully used in an different project with another uP TMS570LS3137.

With the TMS570LC4357-EP this method doesn't work.

How can I do to prevent losing data stored the RAMNOINIT memory?


Best regard.

Domenico

Following the instruction placed in my C source file:

#pragma DATA_SECTION(Watchdog_ResetCounter_g, ".section_noinit")
static Watchdog_ResetCounter_t Watchdog_ResetCounter_g;

Following my linker settings:

/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */
--retain="*(.intvecs)"
-heap 0x800

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */
MEMORY{
    VECTORS         (X)  : origin=0x00000000 length=0x00000020
    FLASH0          (RX) : origin=0x00000020 length=0x001FFFC8
    FLASH1          (RX) : origin=0x00200000 length=0x00200000
    STACKS          (RW) : origin=0x08000000 length=0x00001300
    RAM             (RW) : origin=0x08001300 length=0x0007E000
    versioninfo     (R)  : origin=0x001FFFE8 length=0x00000018
    RAMNONINIT         (RW) : origin = 0x807F300, length = 0xD00
}

/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */
SECTIONS{
    .intvecs : {} > VECTORS
    .text    : {} > FLASH0 | FLASH1
    .const   : {} > FLASH0 | FLASH1
    .cinit   : {} > FLASH0 | FLASH1
    .pinit   : {} > FLASH0 | FLASH1
    .section_versioninfo   : {} > versioninfo
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
    .section_noinit:  > RAMNONINIT, type=NOINIT
}
/*----------------------------------------------------------------------------*/

  • 0
    TI__Guru**** 190806 points

    Hi,

    Domenico Margiotta said:
    How can I do to prevent losing data stored the RAMNOINIT memory?

    I wonder if the reason is because you have a call to _memInit_() in your startup file that clears out the RAM? Can you check?

  • 0
    Guru 92251 points
    Domenico Margiotta said:
    How can I do to prevent losing data stored the RAMNOINIT memory?

    At what point in the code are you checking the data stored in the RAMNOINIT memory?

    The HALCoGen generated _c_int00() function for a  TMS570LC4357 calls the _memInit_() function when the reset source is either:

    • POWERON_RESET
    • DEBUG_RESET
    • EXT_RESET

    Where _memInit_() performs "auto hardware initalisation for SRAM"

  • 0
    Prodigy 40 points

    Thank you for the answer   and @Chester Gillon. The code is generated form the halcogen and the _c_int00 fucntion has not been  modified and the _memInit_ function is present in the switch case POWERON_RESET, DEBUG_RESET and EXT_RESET. If I remove the _memInit_  function in the case DEBUG_REST and EXT_RESET my global variable Watchdog_ResetCounter_g after a reset the values is cleared.

    The data in RAMNOINIT memory is checked after the initialization phase. For this I put the global variable also before the _memInit_ call, but the data is cleared too.

    Any idea?

    Best regards

  • 0 in reply to Domenico Margiotta
    Prodigy 40 points

    Hello,

    continuing with the debug, I have noted that the function _cacheEnable_ clears the values in the RAMNOINIT memory. Commenting this, all works when the uP is reset by the JTAG but when I run the SW without it, the section RAMNOINIT continues to be cleared

    1) What is the functionality of _cacheEnable_()? And what is the behavior of the uP with or without the _cacheEnable_? 

    2) Should the _memInit_ function remain commented in the DEBUG_RESET/EXT_RESET cases?

    Thank you.

  • +1 in reply to Domenico Margiotta
    TI__Guru**** 190806 points

    Hi Domenico,

    Domenico Margiotta said:
    1) What is the functionality of _cacheEnable_()? And what is the behavior of the uP with or without the _cacheEnable_? 

      There is both a 32kB Data cache and Instruction cache on the TMS470LC4357 processor . When you enable cache, it will first invalidate all data in the cache memory. Your data is first stored in the level-2 RAM. As the data is read, it is then stored in cache for fast access in the future. In another word, your Watchdog_ResetCounter_t  is first allocated to level-2 memory. After it is read the first time, it is stored in the cache memory. When you do a reset, the processor starts from _c_init00() and will execute the _cacheEnable_() to invalidate the cache. This is how Watchdog_ResetCounter_t  got cleared out while the level-2 memory is never updated due to the cache write-back scheme. I will suggest you change to write-through scheme so that the level-2 memory is always coherent with the cache memory. When a reset is applied, the cache memory is invalidated but level-2 memory still contains the latest data. However, if you apply _memInit_(), it will clear to the level-2 memory too. Therefore, you will need to disable _memInit_() to avoid resetting level-2 memory. But be careful that after a power cycle, the MCU will come up with random values in the level-2 RAM. You are likely to see ECC error when reading the level-2 RAM. 

    ; Enable caches

    .def _cacheEnable_
    .asmfunc

    _cacheEnable_

    stmfd sp!, {r0-r1}
    mov r0,#0

    MRC p15, #0, R1, c1, c0, #0 ; Read System Control Register configuration data
    ORR R1, R1, #0x1 <<12 ; instruction cache enable
    ORR R1, R1, #0x1 <<2 ; data cache enable
    DSB
    MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache
    DSB ; delay is required, manually added
    MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache
    DSB ; delay is required, manually added
    MCR p15, #0, R1, c1, c0, #0 ; enabled cache RAMs
    ISB

    ldmfd sp!, {r0-r1}

    bx lr
    .endasmfunc

    To change to Write-Through cache, you can update the MPU with below either settings for the level-2 RAM.

  • 0 in reply to Charles Tsai
    Prodigy 40 points

    Thank you very much.

    Now all work fine. In addition there is also an error on our schematic design. The output signal of the external watchgdog is connected to the pin nPORRST and so when it is is deasserted, the function getResetSource() returns always a POWERON_REST value instead of EXT_RESET. So I had to modify the _c_int00 to correctly detect a watchdog reset in order to not run the memInit function.

    Best regards.