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MSP432E401Y: ADC sample issue

Part Number: MSP432E401Y

Hi team,

To achieve a sampling rate of 2 m, the configuration is as follows:

systemClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL | SYSCTL_CFG_VCO_320),
120000000);

ADC0->CC=0x90;

 MAP_TimerLoadSet(TIMER0_BASE, TIMER_A, systemClock/(2000000));

ADC uses pll vco as the clock source, div divided by 10 times, and pll vco of 320 m divided into 32 m. Then trigger with a speed of timer A, 2 m. Take dma and continue to collect 1024 points. Finally, the sampling data was calculated and only 30 k. The customer would like to know what's the possible reason for that.

Could you help check this case? Thanks!

Best Regards,

Cherry