• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 259 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP432E401Y: ADC clock configure issue

Cherry Zhou
Mastermind 22235 points
Part Number: MSP432E401Y

Hi team,

The customer has configured as follows:

ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL,15);
for(x=0;x<2000;x++);
/* Enable the clock to ADC-0 and wait for it to be ready */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
while(!(MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0)))
{
}

And then ADC cannot collect data directly, the customer would like to know how to configure the ADC 32M clock.

Could you help check this issue? Thanks.

Best Regards,

Cherry

  • 0
    TI__Mastermind 22235 points

    Hi,

    May I know is there any updates?
    Thanks and Best Regards,

    Cherry

  • 0
    TI__Mastermind 46685 points

    Hi Cherry,

    Sorry for the late response.

    Please check the following points to configure the ADC with 32M clock in MSP432E TRM chapter 10.3.2.7.

    "The system clock must be at the same frequency or higher than the ADC clock." and "Divided PLL VCO. The PLL VCO frequency can be configured to generate up to a 32-MHz clock for a conversion rate of 2 Msps. The CS field in the ADCCC register must be programmed to 0x0 to select the PLL VCO and the CLKDIV field is used to set the appropriate clock divisor for the desired frequency."

    Best regards,

    Cash Hao