Hi Team,
Seeking for some clarification.
This is a related topic to the known issue of the PLL self test - when the self test is done the PLL output frequency is no longer in the normal operating frequency range of 150 and 550 MHz, thus causing the VCO voltage to drop below 200mV where it is not possible any more to propagate out of the PLL.
We have the following issue with our PLL settings:
- Oscillator Frequency OSCIN = 12.5 MHz
- Reference Clock Divider (NR) = 2
- PLL Multiplication Factor (NF) = 116
The PLLMUL field [15:00] of the PLLCTL1 register is initialized to 0x7300, resulting in an effective value for NF of
NF = 0x7300 / 256 + 1 = 116.
According to the TI's FMzPLL calculator, the VCOCLK frequency is formed as VCOCLK = OSCIN / NR * NF = 725 MHz.
According to the specification of VCOCLK in application note "spns162c", this violates the maximum boundary (550 MHz).
However, the described problem occurs because the lower boundary (150 MHz) is violated at low temperature, causing an amplitude below 200 mV, which causes the PLL to stop operating.
2) Currently the output frequency is 181.25MHz which is above the specified 180MHz à what is the impact here?
Thank you very much.
-Mark
