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TMS570LC4357: TMS570LC43 two CAN channels not working simultaneously.

anil pande
Prodigy 80 points
Part Number: TMS570LC4357

Greetings!

We are using TMS570Lc43 microcontroller - two CAN channels as input.

When we receives data on both channels (separate CAN bus) we observed that after some time only one channel receives data.

What modification  need to be done so that both channels work simultaneously.

Thanks in advance.

Anil 

  • 0
    TI__Guru**** 192486 points

    Hi Anil,

    Please post your configuration for those two CAN modules. The mask bits of IFx Mask Register are used for acceptance filtering. The received messages are stored into their appropriate message objects only if they pass acceptance filtering.

  • 0 in reply to QJ Wang
    Prodigy 80 points

    /** @file HL_can.c
    * @brief CAN Driver Source File
    * @date 11-Dec-2018
    * @version 04.07.01
    *
    * This file contains:
    * - API Functions
    * - Interrupt Handlers
    * .
    * which are relevant for the CAN driver.
    */

    /*
    * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
    *
    *
    * Redistribution and use in source and binary forms, with or without
    * modification, are permitted provided that the following conditions
    * are met:
    *
    * Redistributions of source code must retain the above copyright
    * notice, this list of conditions and the following disclaimer.
    *
    * Redistributions in binary form must reproduce the above copyright
    * notice, this list of conditions and the following disclaimer in the
    * documentation and/or other materials provided with the
    * distribution.
    *
    * Neither the name of Texas Instruments Incorporated nor the names of
    * its contributors may be used to endorse or promote products derived
    * from this software without specific prior written permission.
    *
    * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    */

    /* USER CODE BEGIN (0) */
    /* USER CODE END */


    /* Include Files */

    #include "HL_can.h"
    #include "HL_sys_vim.h"

    /* USER CODE BEGIN (1) */
    uint32_t MessageLength;
    /* USER CODE END */


    /* Global and Static Variables */

    #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
    #else
    static const uint32 s_canByteOrder[8U] = {3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U};
    #endif

    /* USER CODE BEGIN (2) */
    /* USER CODE END */


    /** @fn void canInit(void)
    * @brief Initializes CAN Driver
    *
    * This function initializes the CAN driver.
    *
    */
    /* USER CODE BEGIN (3) */
    /* USER CODE END */
    /* SourceId : CAN_SourceId_001 */
    /* DesignId : CAN_DesignId_001 */
    /* Requirements : HL_CONQ_CAN_SR4 */
    void canInit(void)
    {
    /* USER CODE BEGIN (4) */
    /* USER CODE END */
    /** @b Initialize @b CAN1: */

    /** - Setup control register
    * - Disable automatic wakeup on bus activity
    * - Local power down mode disabled
    * - Disable DMA request lines
    * - Enable global Interrupt Line 0 and 1
    * - Disable debug mode
    * - Release from software reset
    * - Enable/Disable parity or ECC
    * - Enable/Disable auto bus on timer
    * - Setup message completion before entering debug state
    * - Setup normal operation mode
    * - Request write access to the configuration registers
    * - Setup automatic retransmission of messages
    * - Disable error interrupts
    * - Disable status interrupts
    * - Enter initialization mode
    */

    canREG1->CTL = (uint32)0x00000200U
    | (uint32)0x00000020U
    | (uint32)((uint32)0x00000005U << 10U)
    | 0x00020043U;

    /** - Clear all pending error flags and reset current status */
    canREG1->ES |= 0xFFFFFFFFU;

    /** - Assign interrupt level for messages */
    canREG1->INTMUXx[0U] = (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U;

    canREG1->INTMUXx[1U] = (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U;

    /** - Setup auto bus on timer period */
    canREG1->ABOTR = (uint32) 7500U;

    /** - Initialize message 1
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */


    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x00f03456U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 1U;

    /** - Initialize message 2
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x00f13344U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 2U;

    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */
    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x00CA7656U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 3U;

    /** - Initialize message 4
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0xBD1256U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 4U;

    /** - Initialize message 5
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */


    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00f03456U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 5U;

    /** - Initialize message 6
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FFFF00U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00f13344U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 6U;

    /** - Initialize message 7
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00CA7656U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 7U;

    /** - Initialize message 8
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00bd1256U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 8U;

    /** - Initialize message 1
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */


    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0022U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00EC1122U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 25U;//1U;

    /** - Initialize message 2
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0033U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00ECAB33U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 26U;//2U;

    /** - Initialize message 3
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */

    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */
    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0044U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00ECCC44U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 27;//3U;

    /** - Initialize message 4
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0022U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00EB1122U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 28U;

    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */
    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0033U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00EBAB33U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 29;//3U;

    /** - Initialize message 4
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0044U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00EBCC44U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 30U;

    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */
    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00112244U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 31;//3U;

    /** - Initialize message 4
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    // while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    // {
    // } /* Wait */
    //
    // canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0022U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    // canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00EB1122U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    // canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    // canREG1->IF2CMD = (uint8) 0xF8U;
    // canREG1->IF2NO = 28U;

    /** - Setup IF1 for data transmission
    * - Wait until IF1 is ready for use
    * - Set IF1 control byte
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */
    canREG1->IF1CMD = 0x87U;

    /** - Setup IF2 for reading data
    * - Wait until IF1 is ready for use
    * - Set IF1 control byte
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */
    canREG1->IF2CMD = 0x17U;

    /** - Setup bit timing
    * - Setup baud rate prescaler extension
    * - Setup TSeg2
    * - Setup TSeg1
    * - Setup sample jump width
    * - Setup baud rate prescaler
    */
    canREG1->BTR = (uint32)((uint32)0U << 16U) |
    (uint32)((uint32)(4U - 1U) << 12U) |
    (uint32)((uint32)((6U + 4U) - 1U) << 8U) |
    (uint32)((uint32)(4U - 1U) << 6U) |
    (uint32)9U;

    /** - CAN1 Port output values */
    canREG1->TIOC = (uint32)((uint32)1U << 18U )
    | (uint32)((uint32)1U << 17U )
    | (uint32)((uint32)1U << 16U )
    | (uint32)((uint32)1U << 3U )
    | (uint32)((uint32)1U << 2U )
    | (uint32)((uint32)0U << 1U );

    canREG1->RIOC = (uint32)((uint32)1U << 18U )
    | (uint32)((uint32)1U << 17U )
    | (uint32)((uint32)1U << 16U )
    | (uint32)((uint32)1U << 3U )
    | (uint32)((uint32)0U << 2U )
    | (uint32)((uint32)0U <<1U );

    /** - Leave configuration and initialization mode */
    canREG1->CTL &= ~(uint32)(0x00000041U);


    /** @b Initialize @b CAN2: */

    /** - Setup control register
    * - Disable automatic wakeup on bus activity
    * - Local power down mode disabled
    * - Disable DMA request lines
    * - Enable global Interrupt Line 0 and 1
    * - Disable debug mode
    * - Release from software reset
    * - Enable/Disable parity or ECC
    * - Enable/Disable auto bus on timer
    * - Setup message completion before entering debug state
    * - Setup normal operation mode
    * - Request write access to the configuration registers
    * - Setup automatic retransmission of messages
    * - Disable error interrupts
    * - Disable status interrupts
    * - Enter initialization mode
    */
    canREG2->CTL = (uint32)0x00000200U
    | (uint32)0x00000020U
    | (uint32)((uint32)0x00000005U << 10U)
    | 0x00020043U;

    /** - Clear all pending error flags and reset current status */
    canREG2->ES |= 0xFFFFFFFFU;

    /** - Assign interrupt level for messages */
    canREG2->INTMUXx[0U] = (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U;

    canREG2->INTMUXx[1U] = (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U
    | (uint32)0x00000000U;


    /** - Setup auto bus on timer period */
    canREG2->ABOTR = (uint32)7500U;


    /** - Initialize message 1
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */


    canREG2->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00f03456U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF1CMD = (uint8) 0xF8U;
    canREG2->IF1NO = 1U;

    /** - Initialize message 2
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FFFF00U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00f13344U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF2CMD = (uint8) 0xF8U;
    canREG2->IF2NO = 2U;

    /** - Initialize message 3
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00CA7656U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF1CMD = (uint8) 0xF8U;
    canREG2->IF1NO = 3U;

    /** - Initialize message 4
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00bd1256U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF2CMD = (uint8) 0xF8U;
    canREG2->IF2NO = 4U;

    /** - Initialize message 5
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */


    canREG2->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x00f03456U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF1CMD = (uint8) 0xF8U;
    canREG2->IF1NO = 5U;

    /** - Initialize message 6
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x00f13344U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF2CMD = (uint8) 0xF8U;
    canREG2->IF2NO = 6U;

    while ((canREG2->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */
    canREG2->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x00CA7656U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF1CMD = (uint8) 0xF8U;
    canREG2->IF1NO = 7U;

    /** - Initialize message 8
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0xBD1256U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF2CMD = (uint8) 0xF8U;
    canREG2->IF2NO = 8U;

    /** - Initialize message 25
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */


    canREG2->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0022U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00EC1122U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF1CMD = (uint8) 0xF8U;
    canREG2->IF1NO = 25U;

    /** - Initialize message 26
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0033U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00ECAB33U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF2CMD = (uint8) 0xF8U;
    canREG2->IF2NO = 26U;

    /** - Initialize message 27
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0044U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00ECCC44U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF1CMD = (uint8) 0xF8U;
    canREG2->IF1NO = 27;//3U;

    /** - Initialize message 28
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0022U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00EB1122U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF2CMD = (uint8) 0xF8U;
    canREG2->IF2NO = 28;//4U;
    /** - Initialize message 29
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0033U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00EBAB33U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF1CMD = (uint8) 0xF8U;
    canREG2->IF1NO = 29;//3U;

    /** - Initialize message 30
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0044U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00EBCC44U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF2CMD = (uint8) 0xF8U;
    canREG2->IF2NO = 30U;

    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG2->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00FF0000U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x00112244U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG2->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG2->IF1CMD = (uint8) 0xF8U;
    canREG2->IF1NO = 31;//3U;


    /** - Setup IF1 for data transmission
    * - Wait until IF1 is ready for use
    * - Set IF1 control byte
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */
    canREG2->IF1CMD = 0x87U;

    /** - Setup IF2 for reading data
    * - Wait until IF1 is ready for use
    * - Set IF1 control byte
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG2->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */
    canREG2->IF2CMD = 0x17U;

    /** - Setup bit timing
    * - Setup baud rate prescaler extension
    * - Setup TSeg2
    * - Setup TSeg1
    * - Setup sample jump width
    * - Setup baud rate prescaler
    */
    canREG2->BTR = (uint32)((uint32)0U << 16U) |
    (uint32)((uint32)(4U - 1U) << 12U) |
    (uint32)((uint32)((6U + 4U) - 1U) << 8U) |
    (uint32)((uint32)(4U - 1U) << 6U) |
    (uint32)9U;


    /** - CAN2 Port output values */
    canREG2->TIOC = (uint32)((uint32)1U << 18U )
    | (uint32)((uint32)1U << 17U )
    | (uint32)((uint32)1U << 16U )
    | (uint32)((uint32)1U << 3U )
    | (uint32)((uint32)1U << 2U )
    | (uint32)((uint32)0U << 1U );

    canREG2->RIOC = (uint32)((uint32)1U << 18U )
    | (uint32)((uint32)1U << 17U )
    | (uint32)((uint32)1U << 16U )
    | (uint32)((uint32)1U << 3U )
    | (uint32)((uint32)0U << 2U )
    | (uint32)((uint32)0U <<1U );

    /** - Leave configuration and initialization mode */
    canREG2->CTL &= ~(uint32)(0x00000041U);

  • 0 in reply to anil pande
    TI__Guru**** 192486 points

    Can you tell me which mailbox of CAN1 and CAN2 are used for receiving message in your test? What is the message ID? How many CAN nodes on your CAN network? 

    From CAN1 configuration, the mailbox[4:1] are configured for TX message, and the mailbox[8:5] are configured for RX message. The mailboxes have different acceptance filtering settings (mask bit).

    From CAN2 configuration, the mailbox[4:1] are configured for RX message, and the mailbox[8:5] are configured for TX message. The mailboxes have different acceptance filtering settings (mask bit).

  • 0 in reply to QJ Wang
    Prodigy 80 points

    Thanks for your reply.

    We are using CANanalyser to send messages on two ports

    Currently, we are checking only one CAN ID - CAN1 - Mailbox 8 and CAN2 Mailbox - 4. (Message ID : 0x00BD1256)

    Single CAN node - two separate  CAN bus.

  • 0 in reply to anil pande
    TI__Guru**** 192486 points

    CAN2 mailbox-4 doesn't get data?

  • 0 in reply to QJ Wang
    Prodigy 80 points

    it gets data. But, issue when both CAN channel transmission is started  at the same time, it will take only.

  • 0 in reply to anil pande
    Prodigy 80 points

    it gets data. But, issue when both CAN channel transmission is started  at the same time, it will take only one (either 1 or 2)

  • 0 in reply to anil pande
    TI__Guru**** 192486 points

    It is expected. When two or more nodes start a message at the same time, the transmitting nodes monitor the bus while they are sending. If a node detects a dominant level when it is sending a recessive level itself, it will immediately quit the arbitration process and become a receiver instead. The arbitration is performed over the whole Arbitration Field and when that field has been sent, exactly one transmitter is left on the bus. This node continues the transmission as if nothing had happened.