I have configured the TMS570LC4357 to enable the FPU and configured the microcontroller coprocessor auxiliary register to enable the generation of the FPU Invalid and divide by zero exceptions. VIM interrupt 47 has been enabled and configured to generate an IRQ interrupt request.
The divide by zero exception operates as expected.
The invalid exception when testing with a NaN seems to work as expected when using or when the FPU generates a signaling NaN. But a quite NaN propagates through the software until a floating point compare with exception instruction is encountered, then the invalid exception is generated.
Is there a method, either by compiler switch or microcontroller configuration, that would force the generation of signaling NaN for all FPU operations? We are using the TI ARM Optimizing C/C++ Compiler
v18.12.0.LTS.
Thanks in advance.
