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TMS570LC4357: DMA Throughput Calculations

Shivam Kakad
Prodigy 115 points
Part Number: TMS570LC4357

Hi Team,

In Our Application based on the TMS570LC4357 processor, we are having the following DMA channels used for the below-mentioned purpose:

SPI1 Rx - DMA Channel 9 - Operated in Slave Mode with Baudrate 10MHz - High Priority channel
SCI3 Rx - DMA Channel 5 - Baudrate 57600 - Low Priority
SCI3 Tx - DMA Channel 4 - Baudrate 57600 - Low Priority
SCI4 Rx - DMA Channel 7 - Baudrate 9600 - Low Priority
SCI4 Tx - DMA Channel 6 - Baudrate 9600 - Low Priority

Here, SPI1 Rx is configured as the highest priority due to its criticality in nature, where we receive the data continuously on this Peripheral. Additionally, in the system, we have configured the Low Priority channels in the Round Robin scheme and High Priority channels in the Fixed scheme as mentioned in the reference manual. However, in the application currently, we are missing one/2 bytes sporadically for the SCI3 Reception i.e. for the DMA Channel 5. We have tried changing the priorities of these DMA Channels but were not been able to get any breakthrough for the same. As there is Only One DMA Engine on this processor, we were suspecting the DMA is getting hogged and sometimes not getting a chance to Receive the data for SCI3. Thus, for further analysis, we wanted to calculate the throughput of the DMA engine by using all these DMA channels with the mentioned data rate. We would like to know is there any method that can help us in calculating the DMA throughput for our application here to resolve this issue?

Regards,

Shivam

  • 0
    TI__Guru**** 196566 points

    Hi Shivam,

    What is the element count and frame count for SPI1 RX DMA transfer? Does SPI1 slave receive the data continuously without interval? 

  • 0 in reply to QJ Wang
    Prodigy 115 points

    Hi Wang, for SPI1 RX DMA Transfer, the Element Count is 1 whereas the Frame Count is 320. And SPI1 Slave receives the data continuously 32 bit in every 125ms, where the bit rate is 8000*32.

  • 0 in reply to Shivam Kakad
    TI__Guru**** 196566 points
    Shivam Kakad said:
    SPI1 Rx - DMA Channel 9 - Operated in Slave Mode with Baudrate 10MHz

    How did you get the bit rate of 8000x32?

    The word length for SPI TX is up to 16-bit, I assume that the element size is 16-bit, and transfer type is frame transfer. 

    Shivam Kakad said:
    And SPI1 Slave receives the data continuously 32 bit in every 125ms

    Does it receive 2 element (16 bit each) every 125ms? 

    Shivam Kakad said:
    the Frame Count is 320

    The DMA transfer will not be interrupted or arbitrated until 320 words (16-bits is element size=16) has been transferred. 

    Did you try the MibSPI? MibSPI1 can support up to 256 buffers (TG0). DMA can transfer 256 words at a time, then service other channels.

  • 0 in reply to QJ Wang
    Prodigy 115 points

    Yes wang, it receives 2 elements every 125ms. and SPI1 here is used only for reception, not transmission, where the frame transfer count is 320, element transfer count is 1 and read/write element size 16bit and transfer type is Frame transfer.

  • 0 in reply to QJ Wang
    Prodigy 115 points

    MibSPI1 for reception using DMA we have not tried, but do we have any reference example so that we can quickly attempt that?

  • 0 in reply to Shivam Kakad
    TI__Guru**** 196566 points

    SCI3 RX receives one byte every 1/57600*10 (assume 2 stop bits) = 173us

    SCI3 TX transmits one byte every 1/9600*10 (assume 2 stop bits) = 173us

    SCI4 RX receives one byte every 1/57600*10 (assume 2 stop bits) = 1040us

    SCI4 TX transmits one byte every 1/57600*10 (assume 2 stop bits) = 1040us

    SPI1 RX gets one frame (1 element) per 150ms (for 1 element)

    And DMA transferring one word from register to SRAM won't take more than 1us. It is not easy for SCI3 RX to loss bytes. Can you share your DMA conf and how you handle the DMA packet?  

  • 0 in reply to QJ Wang
    TI__Guru**** 196566 points

    I just dis a test:

    SPI1 Rx - DMA Channel 9 - Baudrate 10MHz - High Priority channel, fixed priority, Element count=2, Frame Count=1, 16-bit, Frame transfer

    SPI1 Tx - DMA Channel 8 - Baudrate 10MHz - High Priority channel, fixed priority, Element count=2, Frame Count=1, 16-bit, Frame transfer

    SCI3 Rx - DMA Channel 5 - Baudrate 57600 - Low Priority, round-robin, Element count =1, Frame count = 100; 8-bit, Frame transfer

    SCI3 Tx - DMA Channel 4 - Baudrate 57600 - Low Priority, round-robin, Element count =1, Frame count = 100; 8-bit, Frame transfer

    SCI4 Rx - DMA Channel 7 - Baudrate 9600 - Low Priority, round-robin, Element count =1, Frame count = 100; 8-bit, Frame transfer

    SCI4 Tx - DMA Channel 6 - Baudrate 9600 - Low Priority, round-robin, Element count =1, Frame count = 100; 8-bit, Frame transfer

    All the DMA transfer are triggered at the same time. All data were transferred and received correctly. 

  • 0 in reply to QJ Wang
    Prodigy 115 points

    Hi Wang, this is the data we have configured the DMA packets:

    SPI1 Rx - DMA Channel 9 - Baudrate 10MHz - High Priority channel, fixed priority, Element count = 1, Frame Count = 320, 16-bit, Frame transfer, Auto Negotiation ON,

    SCI3 Rx - DMA Channel 5 - Baudrate 57600 - Low Priority, fixed priority, Element count = 1, Frame count = 288; 8-bit, Frame transfer, Auto Negotiation OFF, No Parity, 2-Stop Bits

    SCI3 Tx - DMA Channel 4 - Baudrate 57600 - Low Priority, fixed priority, Element count = 1, Frame count = 0-288; 8-bit, Frame transfer, Auto Negotiation OFF, No Parity, 2-Stop Bits

    SCI4 Rx - DMA Channel 7 - Baudrate 9600 - Low Priority, fixed priority, Element count = 1, Frame count = 288; 8-bit, Frame transfer, Auto Negotiation OFF, Odd Parity, 2-Stop Bits

    SCI4 Tx - DMA Channel 6 - Baudrate 9600 - Low Priority, fixed priority, Element count = 1, Frame count = 0-288; 8-bit, Frame transfer, Auto Negotiation OFF, Odd Parity, 2-Stop Bits

  • 0 in reply to Shivam Kakad
    Prodigy 115 points

    Hi Wang, Are you able to find anything wrong here in the DMA configuration specifically for the SPI Reception over DMA, because as soon as, we are removing(or commenting) the SPI DMA channel configurations, we are properly receiving the data over UART DMA without any CRC corruption as mentioned in this post. Further, SPI used here is receiving the data in the HBCA and BTCA interrupt mode, where the received data is in the form of a sinusoidal wave.

  • 0 in reply to Shivam Kakad
    TI__Guru**** 196566 points

    SPI1 RX only receives 1 Frame per 125ms, right?

  • 0 in reply to QJ Wang
    Prodigy 115 points

    32 bit of data for every 125ms, where transfer type is Frame and access size is 16bit.