I am using PORTL pins 2,3,6,7 as GPIO output with OD , 2ma strength
//PORT L
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOL))
{
}
GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_2); // open drain 2ma
GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_3); // open drain 2ma
GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_6); // open drain 2ma
GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_7); // open drain 2ma
GPIOPadConfigSet(GPIO_PORTL_BASE,GPIO_PIN_2,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_OD);
GPIOPadConfigSet(GPIO_PORTL_BASE,GPIO_PIN_3,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_OD);
GPIOPadConfigSet(GPIO_PORTL_BASE,GPIO_PIN_6,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_OD);
GPIOPadConfigSet(GPIO_PORTL_BASE,GPIO_PIN_7,GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_OD);
Surprisingly the pins 2 and 3 behave as expected but Pins 6 and 7 are behaving as if they are NOT Open Drain and also when I output 0 or 1 to these pins, the actual output on the pins (pin 93 and pin94) are inverted.
As I am using Ethernet , I have this function
// configure Ethernet pins
PinoutSet(true, false);
According to me , this should not disturb PL6 and PL7 as USB is disabled.
There is no RTOS used in the project and CCS version is 8.3.1
Can someone help please.