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TMS570LS3137-EP: EMAC fragmentation

Part Number: TMS570LS3137-EP
Other Parts Discussed in Thread: HALCOGEN

We are using EMAC peripheral in our project for external communication, if the packet size is more than 1500 then we fragment it. As per TRM (29.2.6.5.7 ) the End of Pocket is set by EMAC when the complete packet  is received. 

The question is when the external system sends 2K bytes, it will fragment the EMAC packet as two frames of 1500 bytes and 500 bytes. How does the EMAC peripheral set the EOP flag  in Rx descriptor after receiving all the fragments. 

Thanks,

Subash

  • Hi Subash,

      I see QJ answered your question in this post already. https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1052884/tms570ls3137-ep-emac-data-receive-dma

      The EMAC will set the EOP flag for the descriptor that has fragment that is less than what was initialized by the host. Although I'm not an expert on how EMAC actually work,T I think this is taken care of by the EMAC hardware.  I don't think software needs to intervene in setting this flag during reception. 

    After reset the host must write zeroes to all Rx DMA State head descriptor pointers. The Rx port
    may then be enabled. To initiate packet reception, the host constructs receive queues in
    memory and then writes the appropriate Rx DMA state head descriptor pointer. For each Rx
    buffer descriptor added to the queue, the host must initialize the Rx buffer descriptor values as
    follows:
    ? Write the Next Descriptor Pointer with the 32-bit aligned address of the next descriptor in the
    queue (zero if last descriptor)
    ? Write the Buffer Pointer with the byte aligned address of the buffer data
    ? Clear the Offset field
    ? Write the Buffer Length with the number of bytes in the buffer
    ? Clear the SOP, EOP, and EOQ bits
    ? Set the Ownership bit
    The host enables packet reception on a given channel by writing the address of the first buffer
    descriptor in the queue (nonzero value) to the channel’s head descriptor pointer in the channel’s
    Rx DMA state. When packet reception begins on a given channel, the port fills each Rx buffer
    with data in order starting with the first buffer and proceeding through the Rx queue. If the Buffer
    Offset in the Rx DMA State is nonzero, then the port will begin writing data after the offset

    number of bytes in the SOP buffer. The port performs the following operations at the end of
    each packet reception:
    ? Overwrite the buffer length in the packet’s EOP buffer descriptor with the number of bytes
    actually received in the packet’s last buffer. The host initialized value is the buffer size. The
    overwritten value will be less than or equal to the host initialized value.
    ? Set the EOP bit in the packet’s EOP buffer descriptor.
    ? Set the EOQ bit in the packet’s EOP buffer descriptor if the current packet is the last packet
    in the queue.
    ? Overwrite the packet’s SOP buffer descriptor Buffer Offset with the Rx DMA state value (the
    host initialized the buffer descriptor Buffer Offset value to zero). All non SOP buffer
    descriptors must have a zero Buffer Offset initialized by the host.
    ? Overwrite the packet’s SOP buffer descriptor buffer length with the number of valid data
    bytes in the buffer. If the buffer is filled up, the buffer length will be the buffer size minus
    buffer offset.
    ? Set the SOP bit in the packet’s SOP buffer descriptor.
    ? Write the SOP buffer descriptor Packet Length field.
    ? Clear the Ownership bit in the packet’s SOP buffer descriptor.
    ? Issue an Rx host interrupt by writing the address of the packet’s last buffer descriptor to the
    queue’s Rx DMA State Completion Pointer. The interrupt is generated by the write to the Rx
    DMA State Completion Pointer address location, regardless of the value written.
    On interrupt the host processes the Rx buffer queue detecting received packets by the status of
    the Ownership bit in each packet’s SOP buffer descriptor. If the Ownership bit is cleared then
    the packet has been completely received and is available to be processed by the host. The host
    may continue Rx queue processing until the end of the queue or until a buffer descriptor is read
    that contains a set Ownership bit indicating that the next packet’s reception is not complete. The
    host determines that the Rx queue is empty when the last packet in the queue has a cleared
    Ownership bit in the SOP buffer descriptor, a set End of Queue bit in the EOP buffer descriptor,
    and the Next Descriptor Pointer in the EOP buffer descriptor is zero.

  • Hi Charles,

    Thank you so much for your quick response! QJ replied to my different query. 

    As my packet size is dynamic and it is beyond 1500 bytes the packet will be fragmented. For example if the packet size is 2000 bytes then the first frame is received 1500 bytes and second frame is received 500 bytes.  How does the EMAC peripheral understand that the impending 500 bytes after receiving 1500 bytes and set EOP flag in Rx descriptor.

    Thanks,

    Subash 

     

  • Hi,

      Please bear in mind that MTU (maximum transfer unit) for one Ethernet frame is about 1500 bytes. This means that if the upper layer protocol datagram exceeds the MTU  bytes, then the host has to fragment the datagram and send it in multiple Ethernet packets. When I say the host, I mean the processor running the TCP/IP upper layer stack.  Whether your incoming packet is 1MB or 2000 bytes, the upper layer TCP/IP stack will take care of breaking them into packets. In the case of 2000 bytes, I would image TCP/IP stack breaks it into 1500 and 500 bytes of two different Ethernet packets. These two Ethernet packets would take up two receive descriptors in a linked list (packet A with 1500 bytes link to the next descriptor of 500 bytes). In the second descriptor, the packet length is equal to 500. Since it is less than the maximum, EMAC should know to set the SOP and EOP flags in the descriptor. Another way of answering the question would be to ask what happens if the incoming data from another node is only 500 bytes instead of 2000. EMAC should know that it is less than the max and set both SOP and EOP on the same descriptor. 

      Sorry, I don't know how EMAC is actually designed. I answer based on how I suppose it should work. 

  • Hi Charles, 

    As per TRM example, if the transmit side fragments 1514 bytes itself into three fragments as 512, 502 and 500 bytes, how does the receive side EMAC will  exactly sets the EOP flag upon receiving third fragment. Because all the three fragments are less than the 1500 bytes (EMAC max payload).

  • Hi Subash,

      I think the diagram shows what the hardware can support. But I'm not sure this is how the host software will setup the receive buffer descriptors. The hardware does not know how/when/why to create the three fragments of 512, 502 and 500 bytes. So this must be setup by the host software.  If the host software really wanted to setup fragmented buffer descriptors, I would image it will specify the buffer size for each descriptor such as 512, 502 and 500. When a packet length of 1514 bytes is received, it will fill each of the three Rx buffers with data in order starting with the first buffer and proceeding through the Rx queue. Note only the first buffer descriptor will have SOP while the next two buffers will not. I suppose EMAC has the intelligence to know that a 1514-byte packet will only end at the third buffer. It will hence only set the EOP on the third buffer descriptor. I think you just need to believe this is what is going to happen. I have no visibility to the actual circuit to know the algorithm to know the exact condition when EOP is set for the last buffer descriptor. If you really want to prove if this is true or not then you will need to create your own driver. I don't think the stock HalCoGen generated EMAC driver is doing the fragmentation. 

      Again, my knowledge to the actual EMAC hardware is limited. I try to answer to the best of what I expect it to behave.  I also don't understand why do you need to know this level of detail. Are you creating your own driver? Are you creating your own TCP/IP stack?