TMS570LC4357: PBIST self-check

Hi Tirumala,

It is at the same location. The address offset is 0x168.

When you use this function for LC43x, please change the clock for PBIST test, and delay time (64 clock cycles). This is my function for PBIST on LC43x device:

/* Self check for PBIST controller */
void PBIST_SelfCheck(void)
{
volatile uint32 i = 0U;
uint32 index;
uint32 PBIST_wait_done_loop = 0U;

/* Run a diagnostic check on the memory self-test controller */
/* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */

// Step 1:
/* Disable PBIST clocks and ROM clock */
pbistREG->PACT = 0x0U;

// Step 2:
// ROM clock source is GCLK1 divided by 4. PBIST will reset for 64 VBUS cycles
// Maximum PBIST ROM_CLK frequency supported is 82.5MHz.
// Memory self-test controller is disabled
systemREG1->MSTGCR &= 0xFFFFFCF0UL;
systemREG1->MSTGCR |= 0x00000205UL;

// Step 3:
// Global memory hardware initialization is disabled
systemREG1->MINITGCR = 0x5U;

// Step 4:
// Memory self-test controller is enabled
systemREG1->MSTGCR &= 0xFFFFFFF0UL;
systemREG1->MSTGCR |= 0xAUL;

// Step 5:
// Memory self-test run complete status: Memory self-test is not completed
systemREG1->MSTCGSTAT = 0x1U;

// Step 6:
// PBIST controller is enabled
systemREG1->MSINENA = 0x1U;

// Step 7:
// Wait for 64 VBUS clock cycles at least, based on HCLK to VCLK ratio
#define VBUS_CLK_CYCLES 64U
for (index = 0UL; index < (VBUS_CLK_CYCLES + (VBUS_CLK_CYCLES * 1u)); index++);

// Step 8:
// Enable PBIST internal clocks.
pbistREG->PACT = 0x1UL;

// Step 9:
// CPU control of PBIST, setting this bit allows the host processor to
// configure the PBIST controller registers
pbistREG->DLR = 0x10UL;

// Step 10:
// TODO: Custom always fail algorithm, this will not use the ROM and just set a fail
// Ram Group Select: 0
// Return Data Select: 0
// Data Width Register: 2
// Sense Margin Select Register: 0
// Pipeline Latency Select: 0
// RAM Latency Select: 0
pbistREG->RAMT = 0x00002000UL;
*(volatile uint32 *)0xFFFFE400U = 0x4C000001U;
*(volatile uint32 *)0xFFFFE440U = 0x00000075U;
*(volatile uint32 *)0xFFFFE404U = 0x4C000002U;
*(volatile uint32 *)0xFFFFE444U = 0x00000075U;
*(volatile uint32 *)0xFFFFE408U = 0x4C000003U;
*(volatile uint32 *)0xFFFFE448U = 0x00000075U;
*(volatile uint32 *)0xFFFFE40CU = 0x4C000004U;
*(volatile uint32 *)0xFFFFE44CU = 0x00000075U;
*(volatile uint32 *)0xFFFFE410U = 0x4C000005U;
*(volatile uint32 *)0xFFFFE450U = 0x00000075U;
*(volatile uint32 *)0xFFFFE414U = 0x4C000006U;
*(volatile uint32 *)0xFFFFE454U = 0x00000075U;
*(volatile uint32 *)0xFFFFE418U = 0x00000000U;
*(volatile uint32 *)0xFFFFE458U = 0x00000001U;

// Step 11:
// TODO: Run PBIST
//00001 Start / Time Stamp mode restart
//00010 Resume / Emulation read
//00100 Stop
//01000 Step / Step for emulation mode
//10000 Check MISR mode
pbistREG->rsvd1[1U] = 0x1U;

// Step 12:
// Wait until memory self-test done is indicated
while ((systemREG1->MSTCGSTAT & 0x1U) != 0x1U)
{
PBIST_wait_done_loop++;
}/* Wait */

/* Check for the failure */
index = pbistREG->FSRF0 & 0x1U;
if ((pbistREG->FSRF0 & 0x1U) != 0x1U)
{
/* No failure was indicated even if the always fail algorithm was run*/
selftestFailNotification(PBISTSELFCHECK_FAIL1);
}
else
{
/* Check that the algorithm executed in the expected amount of time. */
/* This time is dependent on the ROMCLKDIV selected above */
if (PBIST_wait_done_loop >= 2U)
{
selftestFailNotification(PBISTSELFCHECK_FAIL2);
}

/* Disable PBIST clocks and ROM clock */
pbistREG->PACT = 0x0U;

/* Disable PBIST */
systemREG1->MSTGCR &= 0xFFFFFFF0U;
systemREG1->MSTGCR |= 0x5U;
}

// Step 13:
// Disable PBIST clocks and ROM clock
pbistREG->PACT = 0x0UL;

// Step 14:
// Disable PBIST
systemREG1->MSTGCR &= 0xFFFFFFF0UL;
systemREG1->MSTGCR |= 0x5UL;

// Step 15:
//return ret_val;
}

Thank you!