TMS570LS1114: tiarmclang: wrong assembly output for simple assignment!!!

Mazen Osama

Part Number: TMS570LS1114
Other Parts Discussed in Thread: HALCOGEN, TMS570LC4357

i have the following code snippet exported from HALCoGen Version 04.05.01:

from the sys_startup.c file:

/* Release the MibSPI1 modules from local reset.
     * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
     */
     mibspiREG1->GCR0 = 0x1U;

/**
.
.
other code (unrelated to SPI)
.
.
*/

/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
    { 
    }/* Wait */

the line which makes the simple assignment for the nRESET bit in the GCR0 is assembeled as follows:

mibspiREG1->GCR0 = 0x1U;
0002a604:   E5810000            str        r0, [r1]
0002a608:   E30F1800            movw       r1, #0xf800
0002a60c:   E34F1FF7            movt       r1, #0xfff7

notice that there is no immediate value for the value 1 or anything. using a debugger reveals that surely the GCR0 register is not assigned the value 1 as instructed by the C-code!!!

this leads to the polling on the flag to be an infinite loop causing a system halt right on the startup code.

the same line compiled using TI_ARM_V20.2.5LTS gives the following assembly code:

 mibspiREG1->GCR0 = 0x1U;
0002b0a8:   E59F00C0            ldr        r0, [pc, #0xc0]
0002b0ac:   E3A0C001            mov        r12, #1
0002b0b0:   E580C000            str        r12, [r0]

which actually loads an immediate value of 1 to the correct location and the application works fine!!!

so my question is:

this is just a very basic thing for a compiler to do, so is there any command line argument that can fix this or an attribute that should be applied on the struct? note that this is an exported code from HALCoGen so it's not a code that a developer has wrote, and it was working fine before!!

over 4 years ago

0 QJ Wang over 4 years ago

TI__Guru**** 199096 points

Hi Mazen,

There is no problem with the code generated by HalCoGen. I haven't tried Clang compiler for Hercules devices. Would you please check this issue in CS/Compiler forum?

0 Chester Gillon over 4 years ago

Guru 92251 points

Mazen Osama said:
notice that there is no immediate value for the value 1 or anything. using a debugger reveals that surely the GCR0 register is not assigned the value 1 as instructed by the C-code!!!

I have had a look, using the mibspiInit function generated by HALCoGen 04.07.01 for a TMS570LC4357.

The initial statements in the mibspiInit function are the following, with the first one at source file line 70:

    mibspiREG1->GCR0 = 0U;
    mibspiREG1->GCR0 = 1U;

If use the TI ARM compiler v20.2.5.LTS with --opt_level=off and --keep_asm to keep the generated assembler, the generated assembler is:

	.dwpsn	file "../source/HL_mibspi.c",line 70,column 5,is_stmt,isa 2
        LDR       A1, $C$CON1           ; [DPU_V7R4_PIPE0] |70| 
        MOV       V9, #0                ; [DPU_V7R4_PIPE0] |70| 
        STR       V9, [A1, #0]          ; [DPU_V7R4_PIPE0] |70| 
	.dwpsn	file "../source/HL_mibspi.c",line 71,column 5,is_stmt,isa 2
        LDR       A1, $C$CON1           ; [DPU_V7R4_PIPE0] |71| 
        MOV       V9, #1                ; [DPU_V7R4_PIPE0] |71| 
        STR       V9, [A1, #0]          ; [DPU_V7R4_PIPE0] |71| 

<snip>
	.sect	".text"
	.align	4
||$C$CON1||:	.bits		0xfff7f400,32

And so from the generated assembler you can see the instructions for the register writes are ordered after the line number of the source statement.

If use TI Clang v1.3.0.LTS with -O=0 (disable optimisation) and -save-temps to keep the generated assembler, the generated assembler is:

	movw	r2, #62464
	movt	r2, #65527
	mov	r0, #0
.Ltmp0:
	.loc	7 70 41 prologue_end            @ ../source/HL_mibspi.c:70:41
	str	r0, [r2]
	mov	r1, #1
	.loc	7 71 41                         @ ../source/HL_mibspi.c:71:41
	str	r1, [r2]
	movw	r2, #62576
	movt	r2, #65527
	.loc	7 74 78                         @ ../source/HL_mibspi.c:74:78

The TI Clang compiler has inserted instructions to write 0 and then 1 to mibspiREG1->GCR0, but the instructions to setup the register address (r2) and the value to write (r0 or r1) are shown before the source statement. I.e. as far as can tell the TI Clang compiler has generated the expected instructions, but there is skew between the instructions and the source file .loc used to encode the source statement to instructions for the debugger.

Does that explain the issue you are seeing?

If not please follow the directions in the article How to Submit a Compiler Test Case.

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TMS570LS1114: tiarmclang: wrong assembly output for simple assignment!!!