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RM48L952: Clock - safety diagnostics

Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

HI,

Please clarify the below doubts on the Clock module.

S.No Device Test identifier Clarifications
1 Clock CLK1 Whether ESM Group 1 and Channel 11 event generated?
2 CLK2 Whether ESM Group 1 and Channel 10 event generated?
3 CLK3 Which ESM group and channel event is generated?
4 CLK4 How to export the internal clock via ECLK pin in software? Is it required any halcogen configuration? Please provide APIs for enabling and testing the clock output via ECLK?
5 CLK5 Internal watchdog - Is it possible to stop the soft (warm) reset, when the internal watchdog overflow occurs?
6 CLK8 How to test the DCC functionality via software? How to program good and bad clock ratios and check for the expected results in software? Please provide API details and examples?
7 CLK9,CLK10 How to perform the software test for DWD operation without the watchdog reset.
  • Hello,

    CLK1 Whether ESM Group 1 and Channel 11 event generated?

    Yes, ESM 1.10 is generated. The LPO Clock Detect module consists of a clock monitor (CLKDET) and an internal low power oscillator (LPO). The LPO provides two different clock sources: CLK80K and CLK10M. The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL),  switches all clock domains sourced by OSCIN to the CLK10M clock, and generate the clock monitor interrupt (ESM1.11).

    CLK2 Whether ESM Group 1 and Channel 10 event generated?

    Yes, ESM 1.10 for PLL1 slip and ESM 1.42 for PLL2 slip

    CLK3 Which ESM group and channel event is generated?

    ESM 1.30 if DCC1 error occurs

    ESM 1.52 if DCC2 error occurs

  • Will answer #4/5/8/9/10 tomorrow.

  • Hi Wang,

    Could you please respond to the remaining points.

  • CLK4:

    The ECLK can be enabled from HALCoGen GUI:

    The code is in sysInit() function:

    /** - set ECLK pins functional mode */
    systemREG1->SYSPC1 = 1U;

    /** - set ECLK pins default output value */
    systemREG1->SYSPC4 = 0U;

    /** - set ECLK pins output direction */
    systemREG1->SYSPC2 = 1U;

    /** - set ECLK pins open drain enable */
    systemREG1->SYSPC7 = 0U;

    /** - set ECLK pins pullup/pulldown enable */
    systemREG1->SYSPC8 = 0U;

    /** - set ECLK pins pullup/pulldown select */
    systemREG1->SYSPC9 = 1U;

    /** - Setup ECLK */
    systemREG1->ECPCNTL = (uint32)((uint32)0U << 24U)
    | (uint32)((uint32)0U << 23U)
    | (uint32)((uint32)(8U - 1U) & 0xFFFFU);

  • CLK5 (watchdog):

    You can choose to generate a system reset or a nonmaskable interrupt to the CPU in case of a watchdog violation.

    You can use the HAL generated API to change the reaction of the watchdog. The reaction is:

     - Generate_Reset

    or
     - Generate_NMI

    void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size)
    {
    /* USER CODE BEGIN (33) */
    /* USER CODE END */

    /* Clear the violations if already present */
    rtiREG1->WDSTATUS = 0xFFU;

    rtiREG1->WWDSIZECTRL = (uint32) Window_Size;
    rtiREG1->DWDPRLD = (uint32) dwdPreload;
    rtiREG1->WWDRXNCTRL = (uint32) Reaction;

    /* USER CODE BEGIN (34) */
    /* USER CODE END */
    }

  • CLK8 (DCC):

    You can use HALCOGen GUI to configure it:

  • CLK9,CLK10:

    You can configure the reaction to NMI rather than system reset.

  • Hi Wang,

    Thanks for the prompt reply.

  • Hi Wang,

    Is it possible to use DWD (CLK5A) and DWWD (CLK5B) in the same application? If yes, how?

    For, CLK8  - Is only the halcogen configuration is enough for this test?

  • Is it possible to use DWD (CLK5A) and DWWD (CLK5B) in the same application? If yes, how?

    No, The modes are mutually exclusive. You can use one mode or the other but not both at the same time.

    For, CLK8  - Is only the halcogen configuration is enough for this test?

    Yes, the DCC generated by HAlCOGen is fine.