Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN
HI,
Please clarify the below doubts on the Clock module.
| S.No | Device | Test identifier | Clarifications |
| 1 | Clock | CLK1 | Whether ESM Group 1 and Channel 11 event generated? |
| 2 | CLK2 | Whether ESM Group 1 and Channel 10 event generated? | |
| 3 | CLK3 | Which ESM group and channel event is generated? | |
| 4 | CLK4 | How to export the internal clock via ECLK pin in software? Is it required any halcogen configuration? Please provide APIs for enabling and testing the clock output via ECLK? | |
| 5 | CLK5 | Internal watchdog - Is it possible to stop the soft (warm) reset, when the internal watchdog overflow occurs? | |
| 6 | CLK8 | How to test the DCC functionality via software? How to program good and bad clock ratios and check for the expected results in software? Please provide API details and examples? | |
| 7 | CLK9,CLK10 | How to perform the software test for DWD operation without the watchdog reset. |

