TM4C1294KCPDT: DTT3 versus DTi3 3v3 LDO & EMI rejection

Hi Charles,

Charles Tsai said:

Between the two there is no silicon die difference

How DTT3 is 105°C where DTi3 is only 85°C? Something has to be different in the silicon die to allow higher Industrial temperature range does it not?

Sadly only have the one DTi3 and 2 other DTT3 the same EMI counter measures DTi3 are not working on DTT3. The DTT3 was placed with low temp 235°c PB-free solder paste SnAgCu. Only later followed up with iron tip on package pins had no effect to stop MCU from locking up.

Ralph Jacobi said:

For the DTT3 there are additional tests at higher temperatures to ensure the part operates to specification at the 105C temperature rating.

Hi Ralph,

Yet the CPU (DTT3) will not reset when EMI level is equal to that of DTi3. Seemingly DTT3 is unqualified for equal EMI conditions DTi3 can sustain? It seems the CPU gets locked refuses to reset until POR. Perhaps a marginal MCU but runs ok 22-25°C until equal EMI level is reached?

Yet the DTi3 watchdog would BOR the MCU if EMI level rose above whatever it was qualified to reject. The BOR watchdog condition is not occurring on this single DTT3. Anyhow since supply chain slow down my noted EMI conditions can be checked against DTi3 prior to manufacturing more DTT3's. Per Charles post will swap out the DTT3 and report any difference noted in the failing PCB.

With regards & Happy Holidays

Hi Ralph,

After a week of trouble shooting surround circuits of the DTT3's (replaced 2 MCU from the same G4 batch), Note worthy DTT3's have a lower VDD resistance (4.15k) than DTi3 (4.5k). The DTT3's ADC channels are easily latched (locked) by the lower VDD impedance and MCU reset (external) becomes inactive.

Likely the DTT3 ADC input channels have dissimilar EMI rejection in the lower VDD resistance when monitored channels >40vdc voltage dividers. That level seems to be the cut off point for ADC channel input via very robust divider (3v3 TVS, ferrites etc..). Yet DTi3 ADC channels operate >190vdc monitoring the same channel circuits without ADC channel (AIN8) latching up, reset failure or watchdog BOR failing.

It seems there is a trade-off for the higher DTT3 industrial temperature range that should be looked at more closely, perhaps update the errata sheet. Note below pictures there are three 150mHz regulators for bucking 40vdc to +15v, +12v, +5v, with TPS73533 (+3v3 LDO) with +4v overshoot clamp to supply MCU VDD.  Might someone at TI confirm DTT3 (certain G4 lots) had a lower VDD ohmic resistance relative to certain package ground pins or perhaps just ADC ground/s and VDD rail pins? At least the DTT3's were level 3 (10% blue) when placed via hot air 235°C Chipquick PB free solder paste. 

Update: Have noticed DTT3's VDD current draw cause LDO (U33) regulator to be warm to the touch, VDD is roughly +3.297v for two DTT3's mounted so far. The four DTT3's were vendor shipped placed black static foam/box. I placed moisture card inside box top cover and between two large decacanth bags with moisture card box exterior for later compare.

The photo posted above shows 2018 purchase date and DTT3's were kept packed and relatively cool (57°F-62°F RH40-45%) since purchase date. The DTT3's and DTi3's tested on above PCB were not ramp soaked rather placed with hot air low temp (235°C) PB free solder paste. The ADC must be reconfigured when AIN8 latches and drops the voltage reading (40v to 0.3v-0.4v ADC0 SS1 step 0) and possibly AIN3, AN4, AIN6 there is no actual variable to view ADC0-SS1 step 1. Often parts of the MCU keep running like NVIC and EMAC0 still send GUI updates via LWIP timer GPTM2 for a while until re-powering MCU is required. 

Mounted DTT3 MCU has good pin wetting:

Genatco said:

  Might someone at TI confirm DTT3 (certain G4 lots) had a lower VDD ohmic resistance relative to certain package ground pins or perhaps just ADC ground/s and VDD rail pins?

The blue potentiometer (20K above photos) oddly had direct result lowering 3v3 LDO ohmic resistance. Recently changed DTi3 20k pot to 100K doing the same for DTT3 made VDD resistance 4.8K well above DTi3 4.5k measured AGND to 3v3 LDO test point TP32.

 The ADC0 SS1 step 0 monitoring DC Bus-voltage >/60V seems to have issue of high PWM duty cycle (>90% low side B drives, GPIO 8mA slew rate) clubbing ADC0 via inductive kickback and ADC0 interrupt handler's cycles. The same PWM duty cycle is NOT affecting DTi3 and same or better EMI suppressions added DTT3 inputs AIN3,4,6,8. I was not searching for DTT3 PWM0 drives leading to ADC0 latch up issues albeit DTi3 has no such condition. 

Hi Charles,

Charles Tsai said:

- How many T3 chips have you tested?

Three so far had similar ADC behavior when PWM duty cycle may hold phase current 1-50ms, sudden MCU lock even on the first pulses. The bus voltage (40-60vdc) ADC ANi8 resistor divider monitors two 680µF caps in parallel to help snub sudden MOSFET switching surges. Funny thing is 40vdc monitor pulses are very audible much more than 60v. Sometimes just a silent whisper on very 1st pulse shuts the MCU down. 

Charles Tsai said:

swapped a T3 device to the I3 board?

Afraid to remove the I3 MCU being solder pads are really weak after removing several for one failure or another.  Besides the I3 is the only PCB working up to 200vdc bus voltage.

Charles Tsai said:

What is the result of ABA swap test?

What is this meaning?

Hi G1,

Genatco said:

Afraid to remove the I3 MCU being solder pads are really weak after removing several for one failure or another.  Besides the I3 is the only PCB working up to 200vdc bus voltage.

Until you can show the ABA swap test results, I have not further guidance. 

Hi Charles,

That is unlikely to occur until production of I3 MCU resumes. However, upon noting above T3 watchdog reset failure it seems to have in part caused random startup crashing higher voltage inductive DC. The PWM startup run code reloads watchdog counts several times inside progressing switch cases. Code was unlocking watchdog disabling interrupt bit via dog control register prior to loading new counts, enabling interrupt bit, locking dog registers once again. Saturday recalled forum Bob mention dog control interrupt bit had no effect, but the global dog interrupt also remained enabled during count reloads.

After removing several dog control register interrupt bit sets/clears the T3 startup handler was behaving with fewer crashes. T3 was able to run 100vdc busvoltage more reliably during switch case changes. Note the I3 runs same external peripheral 170vdc with consistent run starts without crashing same watchdog code.

Wondering if it would be prudent to disable Global dog interrupt prior to reloading counts as the dog control register bit remains enabled?  Oddly setting or clearing dog control register interrupt bit did not have any effect on I3, remains puzzling. The EMI crash part remains random during longer runtime code and still remains T3 condition with the same code updated I3. Oddly the T3 MCU's are drawing bit more VDD current than the I3's do, pulling 3v3 LDO down 2.972v.

Hi Charles,

Yesterday was able to remove i3 MCU from a launch pad (second attempt) 385°C hot air. Only after using bench 1500 Watt Lasco space heater to preheat back side PCB, me too . That solder paste on launch pad must have been 360°C or more.

Anyway the VDD rail is suspect being +2.971v right at the recommended minimal VDD. The slightest EMI bounces the ADC sequencer into latch up. The other i3 PCB has 3v307 - 3v308  VDD rail. Funny thing being SS1 step 1 would often post odd voltage (+439v or 0.3v) as it latched up. 

Hi Charles,

The VDD of the T3 was running at table 27-4 Minimum and Watchdog is set for BOR reset, Table 27-6 P8 VDD_BOR0 reset 2.95v Max, VDDA_BOR0 P6 2.89v. Max. The MCU temperature reaches 40°C and ADC0 starts to cause trouble. VDDA is tide to VDD 3v3 rail voltage is a bit to low it seems.

BTW: After hours of testing I3 replacement MCU ADC0 is more stable (VDD, VDDA=2v97). Note the watchdog BOR threshold (P6/P8) of the T3 seems a bit more raised than the I3 (85°C) and seems a tradeoff exists for 105°C higher temperature range. Especially if VDD, VDDA is not in the nominal zone of table 27-6 and falls near the minimum as both I3 & T3 were executing. 

Charles Tsai said:

I will suggest you look into improving EMC from your board perspective. 

Hi Charles,

Yes it was also an issue T3 suspect causing random PWM module to fault 60vdc tests.