Part Number: TMS570LS3137
Hello there,
I'm trying to generate a double-bit Flash ECC error by issuing a 64-bit read to address 0xF00803F8, according with instruction of SPNU499C para. 5.4.2.5, stating that:
5.4.2.5 Deliberate ECC Errors for FMC ECC Checking
Deliberate single-bit and double-bit errors have been placed in the OTP for checking the FMC ECC
functionality. Any portion of the 64 bits in TI OTP bank 0 location F008 03F0h through F008 03F7h as
shown in Figure 5-6 will generate a single-bit error. Any portion of the 64 bits in TI OTP bank 0 location
F008 03F8h through F008 03FFh as shown in Figure 5-6 will generate a double-bit error.
with the following simple code:
ecc = *(u64 *) 0xF00803F8;
The following this read, ecc is indeed equal to 0x123456789ABCDEF0, as per the manual, so the read is successful at the right address. However, the nERROR pin is not activated and the supposedly generated ESM interrupt to Group2 high priority (unmaskable) at interrupt vector 0 was not entered.
Anything that I've done wrong?
Thanks.
