RM48L952: Primary Flash and Level 1 (L1) Interconnect - safety diagnostics

Monish27 said:

1

Primary Flash and Level 1 (L1) Interconnect

FLA1

Whether SL_Init_ECCFlash need to be called? Whether ESM 1.6 and ESM 3.7 event occurs if the fault is detected?

SL_Init_ECCFLASH(0 API should be called to enable SECDED for main program flash, data flash (EEPROM, bank 7), and OTP. 

ESM 1.6 or ESM 3.7 is set if ECC error (1-bit or 2-bit) occurs.

Monish27 said:

2

FLA2

Whether this will be enabled on reset? Whether ESM 2.16 event occurs if the fault is detected?

Hard Error Cache and Livelock: This feature is enabled at reset and cannot be disabled by the software. Once the livelock error happens, the ESM 2.16 will be set.

Monish27 said:

3

FLA3

Which type of ESM event will occur? And Whether this will be enabled on reset?

The address ECC feature is disabled at reset. You can enable it writing 0x0A to EDACEN field of FEDACCTRL1 register. A failure of a single address line inside of the bank will be treated as an uncorrectable error. ESM 2.4 is set if there is a address parity error.

Monish27 said:

4

FLA4

Whether this will be enabled on reset? Whether ESM 2.4 event occurs if the fault is detected?

This diagnostic is enabled at reset, and can be disabled by writing 0xA to BUS_PAR_DIS key in the FPAR_OVR register. ESM 2.4 will be set if there is parity error.

FLA3: ESM 3.7 rather than ESM 2.4 is set if any error.

Hi Wang, 

Please reply for other doubts.

Hi Wang, 

FLA11 - The test FLASH_ECC_TEST_MODE_2BIT and  FLASH_ADDRESS_ECC_SELF_TEST fails continuously? Is any configuration in Halcogen or initialization required? But the test FLASH_ECC_TEST_MODE_1BIT passed.

Regards,

Monish P

Hi Monish,

No special configuration in AHL is needed to run flash selftest. 2-bit ECC error will result in data abort. Is the ESM 3.7 flag set when performing this test?

Hi Wang,

To test the flash memory CRC, we are pre-calculating the CRC for different memory regions using Code Generation Tools Linker. So, the CRC tables get configured in the Linker Command File (LCF) as part of the configured sections.

And our application needs periodically verify the flash CRC. So we calculate the CRC using the function SL_CRC_Calculate. When we compare the result of this function with the pre-calculated CRC, the values are not the same for different memory regions.

Below are the sys_link.cmd and CRC function (VerifyFlashCRC) for reference. Please suggest the solution to resolve it.

/* sys_link.cmd */

/* Memory Map                                                                 */

MEMORY
{

VECTORS (X) : origin=0x00000000 length=0x00000020
CRCMEM (RX) : origin=0x00000020 length=0x00000100
FLASH0 (RX) : origin=0x00000120 length=0x0017FEE0

STACKS (RW) : origin=0x08000000 length=0x00001800
RAM (RW) : origin=0x08008000 length=0x00028000
PROFILE(RW) : origin=0x08036000 length=0x00008000 /* Added for profiling purposes */
LOG (RW) : origin=0x080053B0 length=0x00002000 /* Added for logging purposes */
FEE (R) : origin=0xF0200000 length=0x00000064 /* For FEE testing, Valid only for sample application */

}

/* Section Configuration */

SECTIONS
{
.intvecs : palign(32), fill =0xffffffff {} > VECTORS crc_table(_flash_crc_table, algorithm=TMS570_CRC64_ISO)
.text : palign(32), fill =0xffffffff {} > FLASH0 crc_table(_flash_crc_table, algorithm=TMS570_CRC64_ISO)
.const : palign(32), fill =0xffffffff {} > FLASH0 crc_table(_flash_crc_table, algorithm=TMS570_CRC64_ISO)
.cinit : palign(32), fill =0xffffffff {} > FLASH0 crc_table(_flash_crc_table, algorithm=TMS570_CRC64_ISO)
.pinit : palign(32), fill =0xffffffff {} > FLASH0

.TI.crctab : palign(32), fill =0xffffffff {} > CRCMEM

.STACK_DATA_svc : {. += 1024;} > STACKS, RUN_START(StackModeSVC)
.STACK_DATA_fiq : {. += 1024;} > STACKS, RUN_START(StackModeFIQ)
.STACK_DATA_irq : {. += 1024;} > STACKS, RUN_START(StackModeIRQ)
.STACK_DATA_abt : {. += 1024;} > STACKS, RUN_START(StackModeABT)
.STACK_DATA_und : {. += 1024;} > STACKS, RUN_START(StackModeUND)
.STACK_DATA_sys : {. += 1024;} > STACKS, RUN_START(StackModeSYS)
.bss : {} > RAM
.data : {} > RAM
.sysmem : {} > RAM

LOG_DATA : START( ulLOGStartAddr ), END( ulLOGEndAddr ) > LOG
PROFILE_DATA : START( ulPROFILEStartAddr ), END( ulPROFILEEndAddr ) > PROFILE
}

/* Function to verify CRC */

uint8 VerifyFlashCRC( void )
{
uint8 result;
uint64 crc;
uint32 n;

result = 1U;

for ( n = 0U; n < _flash_crc_table.num_recs; n++ )
{
    crc = SL_CRC_Calculate( ( uint64 * ) _flash_crc_table.recs[ n ].addr, _flash_crc_table.recs[ n ].size >> 3 );

    Uprintf("\r\nActual data %llu ", _flash_crc_table.recs[ n ].crc_value );
    Uprintf("\r\nCalc data %llu ", CRC);

    if ( crc != _flash_crc_table.recs[ n ].crc_value )
    {
        result = 0U;
        Uprintf("\r\nCRC CAL FAILED ");
    }
}
return result;
}

Below is the output of the test.

Actual data 14517981249150324390
Calc data 14655573721901316870
CRC CAL FAILED

Actual data 16153354990184250073
Calc data 9851407417339559623
CRC CAL FAILED

Actual data 15633881793926657410
Calc data 16389150461312545960
CRC CAL FAILED

Actual data 949195034929158233
Calc data 17259016811486918618

Hi Monish,

Please refer to this app note

https://www.ti.com/lit/an/spna235/spna235.pdf?ts=1644466440743&ref_url=https%253A%252F%252Fwww.google.com%252F

Project source code discussed in the app note can be downloaded from the following URL:

http://www.ti.com/lit/zip/spna235

Hi Wang,

One doubt is CRC calculated by SL_CRC_Calculate  and  Code Generation tool in LCF for different memory regions will be same?

Regards,

Monish P

Hi Wang,

Please provide your suggestion.