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RM48L952: Flash Emulated EEPROM (FEE) - Safety Diagnostics

Monish27
Intellectual 636 points

Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

HI,

Please clarify the below doubts on the Flash Emulated EEPROM (FEE) module.

S.No Device Test identifier Clarifications
1 Flash Emulated
EEPROM
(FEE) 		 FEE1 Whether SL_Init_ECCFlash need to be called?
Whether ESM 1.35 and ESM 1.36 events occur if the fault is detected?
2 FEE2A, FEE2B SL_CRC_Calculate function calculates the CRC using the internal CRC module. Is any Halcogen configuration need to be done for this test?
3 FEE3 Which type of ESM event will occur?
4 FEE4 Whether ECC protection is enabled on boot? Does any API need to be called to enable flash protection? Or is it an Halcogen configuration?
5 FEE7 Which type of ESM event will occur?
6 FEE8 Is FEE_ECC_DATA_CORR_MODE are the correct test types to perform this test?
7 FEE9 Is FEE_ECC_SYN_REPORT_MODE are the correct test types to perform this test?
8 FEE10 Is FEE_ECC_MALFUNCTION_MODE1 are the correct test types to perform this test?
9 FEE11 Is FEE_ECC_MALFUNCTION_MODE2 are the correct test types to perform this test?
10 FEE12 Writing into the emulated EEPROM using F021 flash API.
11 FEE13 How to perform software tests for hardware CRC?
12 FEE14 How to perform this test? Whether this feature is internal to RM48 MCU?

Regards,

Monish P

  • 0
    TI__Mastermind 29868 points

    Hi, our expert is out of the office. Please expect a delayed response.

  • 0 in reply to Frank Livingston
    TI__Guru**** 199146 points
    Monish27 said:
    1 Flash Emulated
    EEPROM
    (FEE)     		 FEE1 Whether SL_Init_ECCFlash need to be called?
    Whether ESM 1.35 and ESM 1.36 events occur if the fault is detected?

    FEE1: FEE Data ECC. The program memory (flash bank 0 and bank 1) is protected by SECDED logic implemented inside the ARM Cortex-R4F CPU. Accesses to the EEPROM emulation flash bank (bank 7) are protected by dedicated SECDED logic inside the flash wrapper. 

    The SECDED logic inside the CPU and flash wrapper is not enabled by default and must be enabled by the application. 

    When the CPU detects an ECC single-, or double-bit error on a read from the flash memory, it signals this on a dedicated “Event” bus. This event bus signaling is also not enabled by default and must be enabled by the application.

    SL_Init_ECCFlash() can be used to enable ECC and Event bus signaling. 

    The ESM 1.35 and 1.36 are the flags for ECC error of FEE flash.

    I will answer other questions later