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RM48L952: SRAM and Level 1 (L1) Interconnect - Safety Diagnotics

Monish27
Intellectual 636 points
Part Number: RM48L952

Hi,

Please clarify the below doubts on the SRAM and Level 1 (L1) Interconnect module.

S.No Device Test identifier Clarifications
1 SRAM and Level 1
(L1)
Interconnect 		 RAM1 Whether SL_Init_ECCTCMRAM need to be called?
Whether ESM 1.26 and ESM 1.28 event occur if the fault is detected? And is there any other ESM fault?
2 RAM2  Whether ESM 2.16 error occurs if the fault is detected?
3 RAM3 Is it detected by ESM errors - 1.26, 1.28?
4 RAM4 Is it detected by ESM errors - 2.10 and 2.18?
5 RAM5 Is it detected by ESM errors - 2.6 and 2.8?
6 RAM6 Whether these diagnostics implemented on the RM48 chip?
7 RAM7A The SL_SelfTest_PBIST function using PBIST_EXECUTE test type for the Ram group PBIST_RAMGROUP_06_ESRAM1, PBIST_RAMGROUP_21_ESRAM5, PBIST_RAMGROUP_22_ESRAM6, PBIST_RAMGROUP_28_ESRAM8.
Which algorithm to choose - March13 N Algo for 1 Port mem — BASELINE TEST ALGO with HIGHEST OVERALL COVERAGE? 
8 RAM7B Is it good to test the RAM periodically at run time using SL_SelfTest_PBIST?
9 RAM8 Whether fault detection through ESM events? IF yes, which ESM event will be triggered?
10 RAM9 Golden CRC and calculated CRC will change when the application runs on the memory. Is my understanding correct? If not, whether the golden and calculated CRC will be the same at run time? 
11 RAM12 To verify the diagnostic functionality, which test type needs to be chosen for SL_SelfTest_SRAM function? 
12 RAM13 To verify the diagnostic functionality, which test type needs to be chosen for SL_SelfTest_SRAM function? 
13 RAM14 Which RAM group needs to be tested for this diagnostic functionality?
14 RAM15 Is it an SW implemenataion? If yes, how the failure is detected?
15 RAM16 Whether SRAM_ECC_ERROR_PROFILING test type need to be chosen for this diagnostic functionality?
16 RAM17 To verify the diagnostic functionality, which test type needs to be chosen for SL_SelfTest_SRAM function? 
17 RAM18 How to perform software tests for hardware CRC?
18 RAM19 How to perform this test? Whether this feature is internal to RM48 MCU?

Regards,

Monish P

  • 0
    TI__Guru**** 196346 points
    Monish27 said:
    1 SRAM and Level 1
    (L1)
    Interconnect     		 RAM1 Whether SL_Init_ECCTCMRAM need to be called?
    Whether ESM 1.26 and ESM 1.28 event occur if the fault is detected? And is there any other ESM fault?

    Yes, the SRAM is protected by ECC (SERDED). The ECC logic for the SRAM is disabled at reset and must be enabled by application. After reset, the event signaling mechanism inside the CPU is disabled. This feature must be enabled by application. SL_Init_ECCTCMRAM is to enable ECC and event export feature.

    The ESM 1.26 and ESM 1.28 are set if correctable ECC error occurs.

    The ESM 3.3 and ESM 3.5 are set if uncorrectable ECC error occurs.

    Monish27 said:
    2 RAM2  Whether ESM 2.16 error occurs if the fault is detected?

    RAM2: Hard Error Cache and Livelock. Livelock is indicated via the ESM 2.16.

  • 0 in reply to QJ Wang
    TI__Guru**** 196346 points
    Monish27 said:
    3 RAM3 Is it detected by ESM errors - 1.26, 1.28?
    4 RAM4 Is it detected by ESM errors - 2.10 and 2.18?

    RAM3: Correctable ECC Profiling. When the correctable ECC error count exceeds a user programmed threshold (RAMTHRESHOLD), an error event (ESM 1.26, ESM 1.28) is signaled to the ESM. This mechanism is disabled by default and must be enabled by application.

    RAM4: Address and Control Bus Parity. Yes, ESM 2.10 and ESM 2.18 are set.

    Monish27 said:
    5 RAM5 Is it detected by ESM errors - 2.6 and 2.8?
    6 RAM6 Whether these diagnostics implemented on the RM48 chip?

    RAM5: Redundant Address Decode. Yes, ESM 2.6 and ESM 2.8 will be set.

    RAM6: Data and ECC Storage in Multiple Physical banks. Yes, each logical SRAM word and its associated ECC code is split and stored in two physical SRAM banks.

  • 0 in reply to QJ Wang
    TI__Guru**** 196346 points
    Monish27 said:
    7 RAM7A The SL_SelfTest_PBIST function using PBIST_EXECUTE test type for the Ram group PBIST_RAMGROUP_06_ESRAM1, PBIST_RAMGROUP_21_ESRAM5, PBIST_RAMGROUP_22_ESRAM6, PBIST_RAMGROUP_28_ESRAM8.
    Which algorithm to choose - March13 N Algo for 1 Port mem — BASELINE TEST ALGO with HIGHEST OVERALL COVERAGE? 
    8 RAM7B Is it good to test the RAM periodically at run time using SL_SelfTest_PBIST?

    RAM7A: March13 N Algo for single Port should be used.

    RAM7B: It is optional. PBIST at startup proves integrity over the entirety of RAM. During application run time, SECDED takes over as the active diagnostic and prevents/notifies of any issues with RAM. The PBIST is a destructive test, and I don't recommend o run BIST at run-time. 

  • 0
    Intellectual 636 points

    Hi Wang,

    The SL_SelfTest_SRAM - SRAM_ECC_ERROR_FORCING_2BIT failed continuously. Any configuration is required to perform this test?

    Regards,

    Monish P

  • 0 in reply to Monish27
    TI__Guru**** 196346 points

    Hi Monish,

    Some diagnostics test, for example SRAM_ECC_ERROR_FORCING_2BIT test, result in data aborts. Does your project have data abort handler? The Data abort handler is not part of the safety diagnostic library.

    When you step through the code, did you get ESM flag set (ESM 3.3 and ESM 3.5) when reading the SRAM content whose ECC bits are flipped intentionally?

  • 0 in reply to QJ Wang
    Intellectual 636 points

    Hi Wang,

    Whether SW can detect the ESM group 3 errors using ESM_ApplicationCallback function?

  • 0 in reply to Monish27
    TI__Guru**** 196346 points

    Hi Monish,

    1. The callback function is:

    void ESM_ApplicationCallback(uint32 grp_channel, uint32 param1, uint32 param2, uint32 param3) in esm_application_callback.c

    This callback function are for esm group 1/2/3. 

    2. you can add breakpoints at line 278 and line 284 in sl_selftest.c to see if the ESM flag is set by reading the memory content whose ECC bits have been flipped:

    The ESM flag is cleared at the end of this function after the selftest is finished.