RM57L843: CPU Interconnect Subsystem – Global error

Cherry Zhou

Part Number: RM57L843
Other Parts Discussed in Thread: LAUNCHXL2-RM57L, HALCOGEN

Hi team,

Here's an issue may need your help:

Using the RM57 chip, a project works well on the demo board LAUNCHXL2-RM57L. However, by burning in the PCB that developed by themselves, when start up, it will report ESM's Group 3 #52 CPU global error, and one of them has the 53 CPU global parity fault.

Power supply for demo board schematic AD VCCAD, VSSAD and reference voltage ADREFHI, ADREFLO is 3.3-V supply. And for the customer's own design, reference voltage ADREFHI, ADREFLO, is a separate 3-V power supply. Will this be the possible reason leading to the error?

Could you help check this case? Thanks.

Best Regards,

Cherry

over 4 years ago

0 QJ Wang over 4 years ago

TI__Guru**** 199026 points

Hi Cherry,

The global error may be caused arbitration or protocol conversion or selftest. The SCR global parity error can also set intermittently after CPU self test.

Please check the device errata:

DEVICE#48 SCR generates Global Parity error after CPU self test completion.

The power supply to ADC or the reference levels (ADREFHI, ADREFLO) for ADC don't generate interconnect global error.

0 Cherry Zhou over 4 years ago in reply to QJ Wang

TI__Mastermind 22235 points

Hi Wang,

Thanks for your help here!

Is there any examples of code for errata? The self-test fault is not cleared in the startup file code generated by HALCOGEN.

GCLK cannot exceed HCLK, with the R5F chip they may wants to get faster. Can GCLK never exceed HCLK? And how to improve GCLK after the self-test?

Thanks and Best Regards,

Cherry

0 QJ Wang over 4 years ago in reply to Cherry Zhou

TI__Guru**** 199026 points

HI Cherry,

The maximum clock rate for the CPU STC self-test is 110 MHz. You can configure GCLK=110 for CPU self-test. After CPU self-test, you can config the PLL to the maximum speed.

0 Cherry Zhou over 4 years ago in reply to QJ Wang

TI__Mastermind 22235 points

Hi Wang,

So the step is: configure GCLK and HCLK to 100, and then the self-test passes. To reconfig PLL, just need to execute the systemInit() generated by HALCOGEN, and then go on to configure, is that right?

Thanks and Best Regards,

Cherry

0 Cherry Zhou over 4 years ago in reply to Cherry Zhou

TI__Mastermind 22235 points

Hi,

May I know is there any updates regarding the question above?

Thanks and regards,

Cherry

0 QJ Wang over 4 years ago in reply to Cherry Zhou

TI__Guru**** 199026 points

Cherry Zhou said:
So the step is: configure GCLK and HCLK to 100, and then the self-test passes. To reconfig PLL, just need to execute the systemInit() generated by HALCOGEN, and then go on to configure, is that right?

Yes.

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RM57L843: CPU Interconnect Subsystem – Global error