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TMS570LC4357: Data Reception over SPI in Multibuffered mode

Shivam Kakad
Prodigy 115 points
Part Number: TMS570LC4357


Hi Team,

For our application on TMS570LC4357 controller, we have external master device, which is connected on the MiBSPI1 peripheral where this device is communicating at baud rate 10MHz and Hercules processor is operating in slave mode. The external device is expected to send the continuous audio stream (1 Sinusoidal cycle = 320 Words; 1 word = 2 byte = 16 bit), where processor is sampling the data as, 160 words in first half cycle and then remaining 160 words in next cycle. 

To achieve this requirement, we wanted to have the two independent buffers like a Ping Pong, holding the 160 words each, where first buffer triggers the other after receiving the first 160 words. As per the manual we can use the SPI in Multibuffered mode where TG0 and TG1 will hold each 160 words. Here we would like to understand which mechanism we can use to trigger the TG1 after the data has been received on TG0, without missing any bytes in between.

Regards,
Shivam

  • 0
    TI__Guru**** 197936 points

    Hi Shivan,

    When MibSPI operates in multi-buffered slave mode, it uses the chip-select pins to generate a trigger to the corresponding TG. For example, putting CS0=LOW triggers TG0, and putting CS0=HIGH triggers TG1.

    In slave mode, only the SPISCS pins can trigger a Transfer Group. The chip-select trigger operates as a level-sensitive trigger. 

  • 0 in reply to QJ Wang
    Prodigy 115 points

    Hi Wang,

    Thanks for your quick response.
    So, In multi buffer slave mode, when the TG0 and TG1 are configured as length 160 each and both TGs are configured as OneShot Transfer, TRG_ALWAYS and TRG_DISABLED, will we be able to receive the data continuously as the external master transmits? And also if we want to enable the Transfer group complete interrupt on TG0 by configuring the SETINTENRDY field of TGITENST, are we expected to get the interrupt after receiving the 160 words from external device?

  • 0 in reply to Shivam Kakad
    TI__Guru**** 197936 points

    the PRST field should be cleared to 0

    Shivam Kakad said:
    TRG_ALWAYS and TRG_DISABLED,

    In slave mode, the trigger source and trigger event are not taken into account by the sequencer. In slave mode, the PRST field should be cleared to 0.

    Shivam Kakad said:
    if we want to enable the Transfer group complete interrupt on TG0 by configuring the SETINTENRDY field of TGITENST, are we expected to get the interrupt after receiving the 160 words from external device?

    Yes, you are correct. If you use both TG0 and TG1, the data will be written to TG0 if CS0=0, and TG1 if CS0=1.

  • 0 in reply to QJ Wang
    Prodigy 115 points

    Slightly confused over here. When you mentioned CS0, does it mean Chip Selects? If Yes, then generally, if we wanted to use TG3 as well then how that will get triggered as 0 and 1 is used for CS0 and CS1 respectively. Actually i was in impression that control to the Transfer Groups will be given as per the Length configured for each group and the LTGPEND value. Please help me in understanding this.

    In Our application we are having Slave Connected to CS1, where actual data from the master will be continuously received by pulling the CS1 Low. We wanted to configure the PCURRENT0 as 0 and PCURRENT1 as 160 for TGxCTRL register, where the LPEND field of LTGPEND register as (320-1). To achieve the TG0 Holding 160 words and generates the Transfer Complete Interrupt for TG0 and then process the next 160 words from TG1; Will it not be possible using this method?

  • 0 in reply to Shivam Kakad
    TI__Guru**** 197936 points
    Shivam Kakad said:
    When you mentioned CS0, does it mean Chip Selects?

    yes, chip-select 0

    Shivam Kakad said:
    if we wanted to use TG3 as well then how that will get triggered as 0 and 1 is used for CS0 and CS1 respectively.

    For TG3, 2 chip selects should be used.

    If you use only one TG, you can use any chip select to trigger the TG. If you use more than 1 TGs, you need to use the encoded and decoded chip selects. Please refer to 28.2.6.7 of device TRM

    PCURRENT of TGxCTRL register is to configure the buffer pointer. 

  • 0 in reply to QJ Wang
    Prodigy 115 points

    Hi Wang,
    Just wanted to clarify as per your previous post, as mentioned earlier, in our application only the CS1 is connected to the external master. So If master pulls CS1 to low and then transmits 160 words then TG0(0000) will get triggered and it will store those 160 words in MiBSPI1 RAM and when master pull CS1 to high, and transmits next 160 words, then TG2(0010) will get triggered.

  • 0 in reply to Shivam Kakad
    Prodigy 115 points

    Hi Wang, 

    We tried configuring the CS as per the requirement, however the first received word (2 bytes) is getting stored in the SPIBUF but not in the MiBSPI RAM, wanted to understand what is going wrong here, even though we are enabling the transfer groups. please find the attached image for the same here.




  • 0 in reply to Shivam Kakad
    TI__Guru**** 197936 points

    Hi Shivam,

    Your understanding is not correct. Please refer to 28.2.6.7 MibSPI Slave in Multi-buffer Configuration of TRM

  • 0 in reply to QJ Wang
    TI__Guru**** 197936 points

    The received data are placed in RX_RAM and RFBUF