TMS570LC4357: How to create a bin file ?

Santhosh Chandramohan

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hi Ti Team/ QJ Wang,

I have issue in size of bin if i use Flash1 (Bank 1) memory for the project or build.

Post-build steps

"${CCS_INSTALL_ROOT}/utils/tiobj2bin/tiobj2bin" "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.bin" "${CG_TOOL_ROOT}/bin/armofd" "${CG_TOOL_ROOT}/bin/armhex" "${CCS_INSTALL_ROOT}/utils/tiobj2bin/mkhex4bin"

VECTORS (X) : origin=0x00000000 length=0x00000020
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0
FLASH1 (RX) : origin=0x00200000 length=0x00200000
STACKS (RW) : origin=0x08000000 length=0x00001500
RAM (RW) : origin=0x08001500 length=0x0007EB00

bin file size is 62k for LED blink , FEE and CAN.

same build with

VECTORS (X) : origin=0x00200020 length=0x00000020
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0
FLASH1 (RX) : origin=0x00200040 length=0x001FFFBF
STACKS (RW) : origin=0x08000000 length=0x00001500
RAM (RW) : origin=0x08001500 length=0x0007EB00

Bin file size is 2049k for same project

LED blink , FEE and CAN functionality.

Please explain the

Thanks in Advance.

Santhosh

over 3 years ago

0 QJ Wang over 3 years ago

TI__Guru**** 197036 points

Hi Santhosh,

If all the code (data and text) are allocated to FLASH1, the size of the bin file should be the same.

SECTIONS
{

.intvecs : {} > VECTORS
.text : {} > FLASH1
.const : {} > FLASH1
.cinit : {} > FLASH1
.pinit : {} > FLASH1
.bss : {} > RAM
.data : {} > RAM
.sysmem : {} > RAM

If they are allocated to FLASH0 AND FLASH1, the size of the binary image will be > size of the first flash bank.

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang.

I have two different Application bin files

1. Simple Application code which consists of LED blinking and CAN messages

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 00010380

I can go to the Application image address (0x00200020) from UART Bootloader and it is working fine

as well as it works Application to bootloader (0x00000000)

2. Complex Application code which consists of almost all functionality like CAN, UART, SPI, I2C and RTI.

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 0003F2B0

But in this application code it doesn't work from UART bootloader to application itself.

Both the Application HL_sys_link.cmd file also same with address.

Please help me to resolve this issue

Thanks in Advance

Santhosh

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

Hi Santhosh,

Is the whole application (complex) programmed to flash successfully? Is the application programed to flash using bootloader?

Can the code execution jump from bootloader to application? From what you provided, it's hard for me to guess what the problem is.

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

Yes whole Application (complex) programmed to flash successfully without bootloader with debug is working fine.

Yes Application programmed to flash using bootloader is also successfully but it doesn't code execution jumps from bootloader to application.

it jumps to address but it doesn't runs application properly.

Thanks in advance.

Santhosh.

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

Hi Santhosh,

Santhosh Chandramohan said:
Yes whole Application (complex) programmed to flash successfully without bootloader with debug is working fine.

I think the application is programmed to flash starting at 0x00000000 using JTAG debugger.

Can you please post the linker cmd file used by application image?

The start address of the application should be 0x200020 rather than 0x200000.

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

I have attached both bootloader and application Linker cmd file .

Bootloader linker cmd file.

/*----------------------------------------------------------------------------*/
/* sys_link.cmd */
/* */
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/* */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Linker Settings */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map */

MEMORY
{
/* USER CODE BEGIN (2) */
#if 0
/* USER CODE END */
VECTORS (X) : origin=0x00000000 length=0x00000020
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0
FLASH1 (RX) : origin=0x00200000 length=0x00200000
STACKS (RW) : origin=0x08000000 length=0x00001500
RAM (RW) : origin=0x08001500 length=0x0007eb00

/* USER CODE BEGIN (3) */
#endif

#if 1
VECTORS (X) : origin=0x00000000 length=0x00000020 fill = 0xffffffff
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0 vfill = 0xffffffff
FLASH1 (RX) : origin=0x00200000 length=0x001FFFBF vfill = 0xffffffff
/* Bank 7 (128kB, FEE) */
FLASH7 (R) : origin=0xF0200000 length=0x00020000 vfill = 0xffffffff

STACKS (RW) : origin=0x08000000 length=0x00001500
RAM (RW) : origin=0x08001500 length=0x0002EB00
/* Bank 0 ECC */
ECC_VEC (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
length=(size(VECTORS) >> 3)
ECC={algorithm=algoL2R5F021, input_range=VECTORS}

ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0) >> 3))
length=(size(FLASH0) >> 3)
ECC={algorithm=algoL2R5F021, input_range=FLASH0 }

/* Bank 1 ECC */
ECC_FLA1 (R) : origin=(0xf0400000 + (start(FLASH1) >> 3))
length=(size(FLASH1) >> 3)
ECC={algorithm=algoL2R5F021, input_range=FLASH1 }

/* Bank 7 ECC */
ECC_FLA7 (R) : origin=0xF0100000
length=(size(FLASH7) >> 3)
ECC={algorithm=algoL2R5F021, input_range=FLASH7 }
#endif
/* USER CODE END */
}

/* USER CODE BEGIN (4) */
#if 1
ECC {
algoL2R5F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
hamming_mask = R4 /* Use R4/R5 build in Mask */
parity_mask = 0x0c /* Set which ECC bits are Even and Odd parity */
mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */
}
#endif
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Section Configuration */

SECTIONS
{
/* USER CODE BEGIN (5) */
#if 0
/* USER CODE END */
.intvecs : {} > VECTORS
.text align(32) : {} > FLASH0 | FLASH1
.const align(32) : {} > FLASH0 | FLASH1
.cinit align(32) : {} > FLASH0 | FLASH1
.pinit align(32) : {} > FLASH0 | FLASH1
.bss : {} > RAM
.data : {} > RAM
.sysmem : {} > RAM

FEE_TEXT_SECTION : {} > FLASH0 | FLASH1
FEE_CONST_SECTION : {} > FLASH0 | FLASH1
FEE_DATA_SECTION : {} > RAM

/* USER CODE BEGIN (6) */
#endif

#if 1
.intvecs : {} palign=8 > VECTORS
flashAPI:
{
.\HALCoGen\source\Fapi_UserDefinedFunctions.obj (.text)
.\Boot\bl_flash.obj (.text)
--library = F021_API_CortexR4_BE_L2FMC.lib (.text)
} palign=8 load = FLASH0, run = RAM, LOAD_START(apiLoadStart), RUN_START(apiRunStart), SIZE(apiLoadSize)

.text : {} palign=8 > FLASH0 /*Initialized executable code and constants*/
.const : {} palign=8 load=FLASH0, run = RAM, LOAD_START(constLoadStart), RUN_START(constRunStart), SIZE(constLoadSize) /*Initialized constant data (e.g. const flash_sectors[..] = )*/
.cinit : {} palign=8 > FLASH0 /* Tables for explicitly initialized global and static variables */
.pinit : {} palign=8 > FLASH0 /* C++ global constructor addresses */
.bss : {} > RAM /* Uninitialized global and static variables */
.data : {} > RAM /* Global and static non-const variables that are explicitly initialized. */
.sysmem : {} > RAM /* Memory pool (heap) for dynamic memory allocation */

FEE_TEXT_SECTION : {} > FLASH0
FEE_CONST_SECTION : {} > FLASH0
FEE_DATA_SECTION : {} > RAM
#endif

/* USER CODE END */
}

/* USER CODE BEGIN (7) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Misc */

/* USER CODE BEGIN (8) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/

Application linker cmd file (Simple)

1. Simple Application code which consists of LED blinking and CAN messages

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 00010380

/* */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Linker Settings */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map */

/* USER CODE BEGIN (3) */
#endif
#if 1
VECTORS (X) : origin=0x00200020 length=0x00000020
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0
FLASH1 (RX) : origin=0x00200040 length=0x001FFFBF
/* Bank 7 (128kB, FEE) */
// FLASH7 (R) : origin=0xF0200000 length=0x00020000 vfill = 0xffffffff
STACKS (RW) : origin=0x08000000 length=0x00001500
RAM (RW) : origin=0x08001500 length=0x0007EB00
/* Bank 0 ECC */

// ECC_VEC (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
// length=(size(VECTORS) >> 3)
// ECC={algorithm=algoL2R5F021, input_range=VECTORS}

// ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0) >> 3))
// length=(size(FLASH0) >> 3)
// ECC={algorithm=algoL2R5F021, input_range=FLASH0 }

/* Bank 1 ECC */
// ECC_FLA1 (R) : origin=(0xf0400000 + (start(FLASH1) >> 3))
// length=(size(FLASH1) >> 3)
// ECC={algorithm=algoL2R5F021, input_range=FLASH1 }

/* Bank 7 ECC */
// ECC_FLA7 (R) : origin=0xF0100000
// length=(size(FLASH7) >> 3)
// ECC={algorithm=algoL2R5F021, input_range=FLASH7 }
#endif

/* USER CODE END */
}

/* USER CODE BEGIN (4) */
#if 0
ECC {
algoL2R5F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
hamming_mask = R4 /* Use R4/R5 build in Mask */
parity_mask = 0x0c /* Set which ECC bits are Even and Odd parity */
mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */
}
#endif
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Section Configuration */

/* USER CODE BEGIN (6) */
#endif

#if 1
.intvecs : {} > VECTORS
.text align(32) : {} > FLASH1
.const align(32) : {} > FLASH1
.cinit align(32) : {} > FLASH1
.pinit align(32) : {} > FLASH1
.bss : {} > RAM
.data : {} > RAM
.sysmem : {} > RAM

FEE_TEXT_SECTION : {} > FLASH1
FEE_CONST_SECTION : {} > FLASH1
FEE_DATA_SECTION : {} > RAM
#endif

#if 0
.intvecs : {} palign=8 > VECTORS
flashAPI:
{
.\source\Fapi_UserDefinedFunctions.obj (.text)
// .\source\BSW\Flash\bl_flash.obj (.text)
--library = F021_API_CortexR4_BE_L2FMC.lib (.text)
} palign=8 load = FLASH1, run = RAM, LOAD_START(apiLoadStart), RUN_START(apiRunStart), SIZE(apiLoadSize)

.text : {} palign=8 > FLASH1 /*Initialized executable code and constants*/
.const : {} palign=8 load=FLASH1, run = RAM, LOAD_START(constLoadStart), RUN_START(constRunStart), SIZE(constLoadSize) /*Initialized constant data (e.g. const flash_sectors[..] = )*/
.cinit : {} palign=8 > FLASH1 /* Tables for explicitly initialized global and static variables */
.pinit : {} palign=8 > FLASH1 /* C++ global constructor addresses */
.bss : {} > RAM /* Uninitialized global and static variables */
.data : {} > RAM /* Global and static non-const variables that are explicitly initialized. */
.sysmem : {} > RAM /* Memory pool (heap) for dynamic memory allocation */

FEE_TEXT_SECTION : {} > FLASH1
FEE_CONST_SECTION : {} > FLASH1
FEE_DATA_SECTION : {} > RAM
#endif

/* USER CODE END */
}

/* USER CODE BEGIN (7) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Misc */

/* USER CODE BEGIN (8) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/

Application linker cmd file: (Complex)

2. Complex Application code which consists of almost all functionality like CAN, UART, SPI, I2C and RTI.

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 0003F2B0

/* */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Linker Settings */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map */

/* USER CODE BEGIN (3) */
#endif
#if 1
VECTORS (X) : origin=0x00200020 length=0x00000020
FLASH0 (RX) : origin=0x00000000 length=0x001FFFE0
FLASH1 (RX) : origin=0x00200040 length=0x001FFFBF
STACKS (RW) : origin=0x08000000 length=0x00001500
RAM (RW) : origin=0x08001500 length=0x0007EB00
#endif

/* USER CODE END */
}

/* USER CODE BEGIN (4) */

/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Section Configuration */

/* USER CODE BEGIN (6) */
#endif

FEE_TEXT_SECTION : {} > FLASH1
FEE_CONST_SECTION : {} > FLASH1
FEE_DATA_SECTION : {} > RAM
#endif

/* USER CODE END */
}

/* USER CODE BEGIN (7) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Misc */

/* USER CODE BEGIN (8) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/

Can I attach the files in this forum is it possible

Please check this linker file and confirm me as soon as possible

Thanks in Advance.

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

I have attached both bootloader and application Linker cmd file .

Bootloader linker cmd file.

/*----------------------------------------------------------------------------*/
/* sys_link.cmd                                                               */
/*                                                                            */
/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
* 
* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/*                                                                            */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
/* USER CODE BEGIN (2) */
#if 0
/* USER CODE END */
    VECTORS (X)  : origin=0x00000000 length=0x00000020
    FLASH0  (RX) : origin=0x00000020 length=0x001FFFE0
    FLASH1  (RX) : origin=0x00200000 length=0x00200000
    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0007eb00

/* USER CODE BEGIN (3) */
#endif

#if 1
    VECTORS (X)  : origin=0x00000000 length=0x00000020  fill = 0xffffffff
    FLASH0  (RX) : origin=0x00000020 length=0x001FFFE0 vfill = 0xffffffff
    FLASH1  (RX) : origin=0x00200000 length=0x001FFFBF vfill = 0xffffffff
    /* Bank 7 (128kB, FEE) */
    FLASH7   (R) : origin=0xF0200000 length=0x00020000 vfill = 0xffffffff

    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0002EB00
/* Bank 0 ECC */
    ECC_VEC  (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
                   length=(size(VECTORS) >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=VECTORS}

    ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0)  >> 3))
                   length=(size(FLASH0)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH0 }

/* Bank 1 ECC */
    ECC_FLA1 (R) : origin=(0xf0400000 + (start(FLASH1)  >> 3))
                   length=(size(FLASH1)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH1 }

/* Bank 7 ECC */
    ECC_FLA7 (R) : origin=0xF0100000
                   length=(size(FLASH7)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH7 }
#endif
/* USER CODE END */
}

/* USER CODE BEGIN (4) */
#if 1
ECC {
    algoL2R5F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
                   hamming_mask = R4         /* Use R4/R5 build in Mask */
                   parity_mask  = 0x0c       /* Set which ECC bits are Even and Odd parity */
                   mirroring    = F021       /* RM57Lx and TMS570LCx are build in F021 */
}
#endif
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
/* USER CODE BEGIN (5) */
#if 0
/* USER CODE END */
    .intvecs : {} > VECTORS
    .text   align(32) : {} > FLASH0 | FLASH1
    .const  align(32) : {} > FLASH0 | FLASH1
    .cinit  align(32) : {} > FLASH0 | FLASH1
    .pinit  align(32) : {} > FLASH0 | FLASH1
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
	
    FEE_TEXT_SECTION  : {} > FLASH0 | FLASH1
    FEE_CONST_SECTION : {} > FLASH0 | FLASH1
    FEE_DATA_SECTION  : {} > RAM

/* USER CODE BEGIN (6) */
#endif

#if 1
   .intvecs    : {} palign=8 > VECTORS
   flashAPI:
   {
      .\HALCoGen\source\Fapi_UserDefinedFunctions.obj (.text)
      .\Boot\bl_flash.obj (.text)
      --library = F021_API_CortexR4_BE_L2FMC.lib (.text)
   } palign=8 load = FLASH0, run = RAM, LOAD_START(apiLoadStart), RUN_START(apiRunStart), SIZE(apiLoadSize)

   .text    : {} palign=8 > FLASH0 /*Initialized executable code and constants*/
   .const   : {} palign=8 load=FLASH0, run = RAM, LOAD_START(constLoadStart), RUN_START(constRunStart), SIZE(constLoadSize)   /*Initialized constant data (e.g. const flash_sectors[..] = )*/
   .cinit   : {} palign=8 > FLASH0 /* Tables for explicitly initialized global and static variables */
   .pinit   : {} palign=8 > FLASH0 /* C++ global constructor addresses */
   .bss     : {} > RAM    /* Uninitialized global and static variables */
   .data    : {} > RAM    /* Global and static non-const variables that are explicitly initialized. */
   .sysmem  : {} > RAM    /* Memory pool (heap) for dynamic memory allocation */

    FEE_TEXT_SECTION  : {} > FLASH0
    FEE_CONST_SECTION : {} > FLASH0
    FEE_DATA_SECTION  : {} > RAM
#endif




/* USER CODE END */
}

/* USER CODE BEGIN (7) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Misc                                                                       */

/* USER CODE BEGIN (8) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/

Application linker cmd file (Simple)

1. Simple Application code which consists of LED blinking and CAN messages

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 00010380

/*----------------------------------------------------------------------------*/
/* sys_link.cmd                                                               */
/*                                                                            */
/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
* 
* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/*                                                                            */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
/* USER CODE BEGIN (2) */
#if 0
/* USER CODE END */
    VECTORS (X)  : origin=0x00000000 length=0x00000020
    FLASH0  (RX) : origin=0x00000020 length=0x001FFFE0
    FLASH1  (RX) : origin=0x00200000 length=0x00200000
    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0007EB00

/* USER CODE BEGIN (3) */
#endif
#if 1
    VECTORS (X)  : origin=0x00200020 length=0x00000020
    FLASH0  (RX) : origin=0x00000000 length=0x001FFFE0
    FLASH1  (RX) : origin=0x00200040 length=0x001FFFBF
        /* Bank 7 (128kB, FEE) */
//    FLASH7   (R) : origin=0xF0200000 length=0x00020000 vfill = 0xffffffff
    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0007EB00
/* Bank 0 ECC */

//    ECC_VEC  (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
//                   length=(size(VECTORS) >> 3)
//                   ECC={algorithm=algoL2R5F021, input_range=VECTORS}

//    ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0)  >> 3))
//                   length=(size(FLASH0)  >> 3)
//                   ECC={algorithm=algoL2R5F021, input_range=FLASH0 }

/* Bank 1 ECC */
//    ECC_FLA1 (R) : origin=(0xf0400000 + (start(FLASH1)  >> 3))
//                   length=(size(FLASH1)  >> 3)
//                   ECC={algorithm=algoL2R5F021, input_range=FLASH1 }

/* Bank 7 ECC */
//    ECC_FLA7 (R) : origin=0xF0100000
//                   length=(size(FLASH7)  >> 3)
//                   ECC={algorithm=algoL2R5F021, input_range=FLASH7 }
#endif

/* USER CODE END */
}

/* USER CODE BEGIN (4) */
#if 0
ECC {
    algoL2R5F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
                   hamming_mask = R4         /* Use R4/R5 build in Mask */
                   parity_mask  = 0x0c       /* Set which ECC bits are Even and Odd parity */
                   mirroring    = F021       /* RM57Lx and TMS570LCx are build in F021 */
}
#endif
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
/* USER CODE BEGIN (5) */
#if 0
/* USER CODE END */
    .intvecs : {} > VECTORS
    .text   align(32) : {} > FLASH0 | FLASH1
    .const  align(32) : {} > FLASH0 | FLASH1
    .cinit  align(32) : {} > FLASH0 | FLASH1
    .pinit  align(32) : {} > FLASH0 | FLASH1
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
	
    FEE_TEXT_SECTION  : {} > FLASH0 | FLASH1
    FEE_CONST_SECTION : {} > FLASH0 | FLASH1
    FEE_DATA_SECTION  : {} > RAM

/* USER CODE BEGIN (6) */
#endif

#if 1
    .intvecs : {} > VECTORS
    .text   align(32) : {} > FLASH1
    .const  align(32) : {} > FLASH1
    .cinit  align(32) : {} > FLASH1
    .pinit  align(32) : {} > FLASH1
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM

    FEE_TEXT_SECTION  : {} > FLASH1
    FEE_CONST_SECTION : {} > FLASH1
    FEE_DATA_SECTION  : {} > RAM
#endif


#if 0
   .intvecs    : {} palign=8 > VECTORS
   flashAPI:
   {
      .\source\Fapi_UserDefinedFunctions.obj (.text)
 //     .\source\BSW\Flash\bl_flash.obj (.text)
      --library = F021_API_CortexR4_BE_L2FMC.lib (.text)
   } palign=8 load = FLASH1, run = RAM, LOAD_START(apiLoadStart), RUN_START(apiRunStart), SIZE(apiLoadSize)

   .text    : {} palign=8 > FLASH1 /*Initialized executable code and constants*/
   .const   : {} palign=8 load=FLASH1, run = RAM, LOAD_START(constLoadStart), RUN_START(constRunStart), SIZE(constLoadSize)   /*Initialized constant data (e.g. const flash_sectors[..] = )*/
   .cinit   : {} palign=8 > FLASH1 /* Tables for explicitly initialized global and static variables */
   .pinit   : {} palign=8 > FLASH1 /* C++ global constructor addresses */
   .bss     : {} > RAM    /* Uninitialized global and static variables */
   .data    : {} > RAM    /* Global and static non-const variables that are explicitly initialized. */
   .sysmem  : {} > RAM    /* Memory pool (heap) for dynamic memory allocation */
   
    FEE_TEXT_SECTION  : {} > FLASH1
    FEE_CONST_SECTION : {} > FLASH1
    FEE_DATA_SECTION  : {} > RAM
#endif


/* USER CODE END */
}

/* USER CODE BEGIN (7) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Misc                                                                       */

/* USER CODE BEGIN (8) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/

Application linker cmd file: (Complex)

2. Complex Application code which consists of almost all functionality like CAN, UART, SPI, I2C and RTI.

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 0003F2B0

/*----------------------------------------------------------------------------*/
/* sys_link.cmd                                                               */
/*                                                                            */
/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
* 
* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/*                                                                            */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
/* USER CODE BEGIN (2) */
#if 0
/* USER CODE END */
    VECTORS (X)  : origin=0x00000000 length=0x00000020
    FLASH0  (RX) : origin=0x00000020 length=0x001FFFE0
    FLASH1  (RX) : origin=0x00200000 length=0x00200000
    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0007EB00

/* USER CODE BEGIN (3) */
#endif
#if 1
    VECTORS (X)  : origin=0x00200020 length=0x00000020
    FLASH0  (RX) : origin=0x00000000 length=0x001FFFE0
    FLASH1  (RX) : origin=0x00200040 length=0x001FFFBF
    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0007EB00
#endif

/* USER CODE END */
}

/* USER CODE BEGIN (4) */

/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
/* USER CODE BEGIN (5) */
#if 0
/* USER CODE END */
    .intvecs : {} > VECTORS
    .text   align(32) : {} > FLASH0 | FLASH1
    .const  align(32) : {} > FLASH0 | FLASH1
    .cinit  align(32) : {} > FLASH0 | FLASH1
    .pinit  align(32) : {} > FLASH0 | FLASH1
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
	
    FEE_TEXT_SECTION  : {} > FLASH0 | FLASH1
    FEE_CONST_SECTION : {} > FLASH0 | FLASH1
    FEE_DATA_SECTION  : {} > RAM

/* USER CODE BEGIN (6) */
#endif

#if 1
    .intvecs : {} > VECTORS
    .text   align(32) : {} > FLASH1
    .const  align(32) : {} > FLASH1
    .cinit  align(32) : {} > FLASH1
    .pinit  align(32) : {} > FLASH1
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM

    FEE_TEXT_SECTION  : {} > FLASH1
    FEE_CONST_SECTION : {} > FLASH1
    FEE_DATA_SECTION  : {} > RAM
#endif

/* USER CODE END */
}

/* USER CODE BEGIN (7) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Misc                                                                       */

/* USER CODE BEGIN (8) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/

I have attached same in code format for your easy understanding

Can I attach the files in this forum is it possible

Please check this linker file and confirm me as soon as possible

Thanks in Advance.

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

Please check the above link.cmd files for the application and bootloader.

Check why it doesn't work?

Thanks in advance.

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

I need a support in Link.cmd file to finish the UART bootloader with application.

Please support me as soon as possible.

I have shared a link.cmd file for bootloader and application.

Thanks in advance.

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

Did I need to check the HL_sys_intvecs.asm file in bootloader and Application file ?

bootloader:

;-------------------------------------------------------------------------------
; HL_sys_intvecs.asm
;
; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
; 
; 
;  Redistribution and use in source and binary forms, with or without 
;  modification, are permitted provided that the following conditions 
;  are met:
;
;    Redistributions of source code must retain the above copyright 
;    notice, this list of conditions and the following disclaimer.
;
;    Redistributions in binary form must reproduce the above copyright
;    notice, this list of conditions and the following disclaimer in the 
;    documentation and/or other materials provided with the   
;    distribution.
;
;    Neither the name of Texas Instruments Incorporated nor the names of
;    its contributors may be used to endorse or promote products derived
;    from this software without specific prior written permission.
;
;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;
;

    .sect ".intvecs"
    .arm

;-------------------------------------------------------------------------------
; import reference for interrupt routines

    .ref _c_int00
    .ref phantomInterrupt
    .def resetEntry

;-------------------------------------------------------------------------------
; interrupt vectors

resetEntry
        b   _c_int00
undefEntry
        b   undefEntry
svcEntry
        b   svcEntry
prefetchEntry
        b   prefetchEntry
dataEntry
        b   dataEntry
        b   phantomInterrupt
        ldr pc,[pc,#-0x1b0]
        ldr pc,[pc,#-0x1b0]

    
;-------------------------------------------------------------------------------

Application:

;-------------------------------------------------------------------------------
; HL_sys_intvecs.asm
;
; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
; 
; 
;  Redistribution and use in source and binary forms, with or without 
;  modification, are permitted provided that the following conditions 
;  are met:
;
;    Redistributions of source code must retain the above copyright 
;    notice, this list of conditions and the following disclaimer.
;
;    Redistributions in binary form must reproduce the above copyright
;    notice, this list of conditions and the following disclaimer in the 
;    documentation and/or other materials provided with the   
;    distribution.
;
;    Neither the name of Texas Instruments Incorporated nor the names of
;    its contributors may be used to endorse or promote products derived
;    from this software without specific prior written permission.
;
;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;
;

    .sect ".intvecs"
    .arm

;-------------------------------------------------------------------------------
; import reference for interrupt routines

    .ref _c_int00
    .ref phantomInterrupt
    .def resetEntry

;-------------------------------------------------------------------------------
; interrupt vectors

resetEntry
        b   _c_int00
undefEntry
        b   undefEntry
svcEntry
        b   svcEntry
prefetchEntry
        b   prefetchEntry
dataEntry
        b   dataEntry
        b   phantomInterrupt
        ldr pc,[pc,#-0x1b0]
        ldr pc,[pc,#-0x1b0]

    
;-------------------------------------------------------------------------------

Both application and bootloader code are same.

Is it okay for bootloader ?

thanks in advance

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

HI QJ Wang,

After I configured my RTI Timer interrupt for my application code. It is not working

In Bootloader RTI Compare0 is configured.

In application I have configured RTI Compare3 after the Application is not working

Thanks in Advance.

Santhosh

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

Hi Santhosh,

There is no problem on my side. My bootloader loads a application (RTI Blinky LED), and application is programmed correctly and the application executes without any problem (LED blinkying). This means that Application can use RTI compare 0/1/2/3.

I am not able to debug your code.

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

Can you please review my sys_link.cmd and HL_sys_intvecs.asm which is posted above message.

Bootloader HL_sys_startup.c

/** @file HL_sys_startup.c 
*   @brief Startup Source File
*   @date 11-Dec-2018
*   @version 04.07.01
*
*   This file contains:
*   - Include Files
*   - Type Definitions
*   - External Functions
*   - VIM RAM Setup
*   - Startup Routine
*   .
*   which are relevant for the Startup.
*/

/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
* 
* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/


/* USER CODE BEGIN (0) */
/* USER CODE END */


/* Include Files */

#include "HL_sys_common.h"
#include "HL_system.h"
#include "HL_sys_vim.h"
#include "HL_sys_core.h"
#include "HL_esm.h"
#include "HL_sys_mpu.h"
#include "HL_errata_SSWF021_45.h"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/* USER CODE BEGIN (2) */
/* USER CODE END */

/* External Functions */

/*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Functions from library" */
extern void __TI_auto_init(void);
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(main should be declared by the user)" */
extern int main(void);
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(Extern declaration present in the library)" */
extern void exit(int _status);


/* USER CODE BEGIN (3) */
/* USER CODE END */
void handlePLLLockFail(void);
/* Startup Routine */
void _c_int00(void);
#define PLL_RETRIES 5U
/* USER CODE BEGIN (4) */
/* USER CODE END */

#pragma CODE_STATE(_c_int00, 32)
#pragma INTERRUPT(_c_int00, RESET)
#pragma WEAK(_c_int00)

/* SourceId : STARTUP_SourceId_001 */
/* DesignId : STARTUP_DesignId_001 */
/* Requirements : HL_CONQ_STARTUP_SR1 */
void _c_int00(void)
{
	register resetSource_t rstSrc;
/* USER CODE BEGIN (5) */
/* USER CODE END */

    /* Initialize Core Registers to avoid CCM Error */
    _coreInitRegisters_();
	
    /* Initialize Stack Pointers */
    _coreInitStackPointer_();

    /* Reset handler: the following instructions read from the system exception status register
     * to identify the cause of the CPU reset.
     */
	rstSrc = getResetSource();
    switch(rstSrc)
    {
        case POWERON_RESET:
		/* Initialize L2RAM to avoid ECC errors right after power on */
		_memInit_();

		/* Add condition to check whether PLL can be started successfully */
        if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U)
		{
			/* Put system in a safe state */
			handlePLLLockFail();
		}
		
/*SAFETYMCUSW 62 S MR:15.2, 15.5 <APPROVED> "Need to continue to handle POWERON Reset" */
        case DEBUG_RESET:
        case EXT_RESET:

/* USER CODE BEGIN (6) */
/* USER CODE END */

        /* Initialize L2RAM to avoid ECC errors right after power on */
		if(rstSrc != POWERON_RESET)
		{
			_memInit_();
		}

/* USER CODE BEGIN (7) */
/* USER CODE END */

/* USER CODE BEGIN (8) */
/* USER CODE END */


/* USER CODE BEGIN (9) */
/* USER CODE END */

        /* Enable CPU Event Export */
        /* This allows the CPU to signal any single-bit or double-bit errors detected
         * by its ECC logic for accesses to program flash or data RAM.
         */
        _coreEnableEventBusExport_();

/* USER CODE BEGIN (10) */
/* USER CODE END */

        /* Check if there were ESM group3 errors during power-up.
         * These could occur during eFuse auto-load or during reads from flash OTP
         * during power-up. Device operation is not reliable and not recommended
         * in this case. */
        if ((esmREG->SR1[2]) != 0U)
        {
           esmGroup3Notification(esmREG,esmREG->SR1[2]);               
        }
	
        /* Initialize System - Clock, Flash settings with Efuse self check */
        systemInit();

/* USER CODE BEGIN (11) */
/* USER CODE END */

        /* Enable IRQ offset via Vic controller */
        _coreEnableIrqVicOffset_();
            
        /* Initialize VIM table */
	    vimInit();

/* USER CODE BEGIN (12) */
/* USER CODE END */
        /* Configure system response to error conditions signaled to the ESM group1 */
        /* This function can be configured from the ESM tab of HALCoGen */
        esmInit();

/* USER CODE BEGIN (13) */
/* USER CODE END */

        break;

        case OSC_FAILURE_RESET:
/* USER CODE BEGIN (14) */
/* USER CODE END */
        break;
		
        case WATCHDOG_RESET:
        case WATCHDOG2_RESET:
				
/* USER CODE BEGIN (15) */
/* USER CODE END */
        break;
    
        case CPU0_RESET:
/* USER CODE BEGIN (16) */
/* USER CODE END */

/* USER CODE BEGIN (17) */
/* USER CODE END */
		
/* USER CODE BEGIN (18) */
/* USER CODE END */

        /* Enable CPU Event Export */
        /* This allows the CPU to signal any single-bit or double-bit errors detected
         * by its ECC logic for accesses to program flash or data RAM.
         */
        _coreEnableEventBusExport_();
		
/* USER CODE BEGIN (19) */
/* USER CODE END */
        break;
    
        case SW_RESET:
		
/* USER CODE BEGIN (20) */
/* USER CODE END */
        break;
    
        default:
/* USER CODE BEGIN (21) */
/* USER CODE END */
        break;
    }

/* USER CODE BEGIN (22) */
/* USER CODE END */

    _mpuInit_();
	
/* USER CODE BEGIN (23) */
/* USER CODE END */

/* USER CODE BEGIN (24) */
/* USER CODE END */


/* USER CODE BEGIN (25) */
/* USER CODE END */

        /* initialize global variable and constructors */
    __TI_auto_init();
/* USER CODE BEGIN (26) */
/* USER CODE END */
    
        /* call the application */
/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
    main();
/* USER CODE BEGIN (27) */
/* USER CODE END */
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
    exit(0);


/* USER CODE BEGIN (28) */
/* USER CODE END */

}

/* USER CODE BEGIN (29) */
/* USER CODE END */

/** @fn void handlePLLLockFail(void)
*   @brief This function handles PLL lock fail.
*/
/* USER CODE BEGIN (30) */
/* USER CODE END */
void handlePLLLockFail(void)
{
/* USER CODE BEGIN (31) */
/* USER CODE END */
	while(1)
	{
		
	}
/* USER CODE BEGIN (32) */
/* USER CODE END */
}
/* USER CODE BEGIN (33) */
/* USER CODE END */

Application HL_sys_startup.c

/** @file HL_sys_startup.c 
*   @brief Startup Source File
*   @date 11-Dec-2018
*   @version 04.07.01
*
*   This file contains:
*   - Include Files
*   - Type Definitions
*   - External Functions
*   - VIM RAM Setup
*   - Startup Routine
*   .
*   which are relevant for the Startup.
*/

/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
* 
* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/


/* USER CODE BEGIN (0) */
/* USER CODE END */


/* Include Files */

#include "HL_sys_common.h"
#include "HL_system.h"
#include "HL_sys_vim.h"
#include "HL_sys_core.h"
#include "HL_esm.h"
#include "HL_sys_mpu.h"
#include "HL_errata_SSWF021_45.h"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/* USER CODE BEGIN (2) */
/* USER CODE END */

/* External Functions */

/*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Functions from library" */
extern void __TI_auto_init(void);
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(main should be declared by the user)" */
extern int main(void);
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(Extern declaration present in the library)" */
extern void exit(int _status);


/* USER CODE BEGIN (3) */
/* USER CODE END */
void handlePLLLockFail(void);
/* Startup Routine */
void _c_int00(void);
#define PLL_RETRIES 5U
/* USER CODE BEGIN (4) */
/* USER CODE END */

#pragma CODE_STATE(_c_int00, 32)
#pragma INTERRUPT(_c_int00, RESET)
#pragma WEAK(_c_int00)

/* SourceId : STARTUP_SourceId_001 */
/* DesignId : STARTUP_DesignId_001 */
/* Requirements : HL_CONQ_STARTUP_SR1 */
void _c_int00(void)
{
	register resetSource_t rstSrc;
/* USER CODE BEGIN (5) */
/* USER CODE END */

    /* Initialize Core Registers to avoid CCM Error */
    _coreInitRegisters_();
	
    /* Initialize Stack Pointers */
    _coreInitStackPointer_();

    /* Reset handler: the following instructions read from the system exception status register
     * to identify the cause of the CPU reset.
     */
	rstSrc = getResetSource();
    switch(rstSrc)
    {
        case POWERON_RESET:
		/* Initialize L2RAM to avoid ECC errors right after power on */
		_memInit_();

		/* Add condition to check whether PLL can be started successfully */
        if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U)
		{
			/* Put system in a safe state */
			handlePLLLockFail();
		}
		
/*SAFETYMCUSW 62 S MR:15.2, 15.5 <APPROVED> "Need to continue to handle POWERON Reset" */
        case DEBUG_RESET:
        case EXT_RESET:

/* USER CODE BEGIN (6) */
/* USER CODE END */

        /* Initialize L2RAM to avoid ECC errors right after power on */
		if(rstSrc != POWERON_RESET)
		{
			_memInit_();
		}

/* USER CODE BEGIN (7) */
/* USER CODE END */

/* USER CODE BEGIN (8) */
/* USER CODE END */


/* USER CODE BEGIN (9) */
/* USER CODE END */

        /* Enable CPU Event Export */
        /* This allows the CPU to signal any single-bit or double-bit errors detected
         * by its ECC logic for accesses to program flash or data RAM.
         */
        _coreEnableEventBusExport_();

/* USER CODE BEGIN (10) */
/* USER CODE END */

        /* Check if there were ESM group3 errors during power-up.
         * These could occur during eFuse auto-load or during reads from flash OTP
         * during power-up. Device operation is not reliable and not recommended
         * in this case. */
        if ((esmREG->SR1[2]) != 0U)
        {
           esmGroup3Notification(esmREG,esmREG->SR1[2]);               
        }
	
        /* Initialize System - Clock, Flash settings with Efuse self check */
        systemInit();

/* USER CODE BEGIN (11) */
/* USER CODE END */

        /* Enable IRQ offset via Vic controller */
        _coreEnableIrqVicOffset_();
            
        /* Initialize VIM table */
	    vimInit();

/* USER CODE BEGIN (12) */
/* USER CODE END */
        /* Configure system response to error conditions signaled to the ESM group1 */
        /* This function can be configured from the ESM tab of HALCoGen */
        esmInit();

/* USER CODE BEGIN (13) */
/* USER CODE END */

        break;

        case OSC_FAILURE_RESET:
/* USER CODE BEGIN (14) */
/* USER CODE END */
        break;
		
        case WATCHDOG_RESET:
        case WATCHDOG2_RESET:
				
/* USER CODE BEGIN (15) */
/* USER CODE END */
        break;
    
        case CPU0_RESET:
/* USER CODE BEGIN (16) */
/* USER CODE END */

/* USER CODE BEGIN (17) */
/* USER CODE END */
		
/* USER CODE BEGIN (18) */
/* USER CODE END */

        /* Enable CPU Event Export */
        /* This allows the CPU to signal any single-bit or double-bit errors detected
         * by its ECC logic for accesses to program flash or data RAM.
         */
        _coreEnableEventBusExport_();
		
/* USER CODE BEGIN (19) */
/* USER CODE END */
        break;
    
        case SW_RESET:
		
/* USER CODE BEGIN (20) */
/* USER CODE END */
        break;
    
        default:
/* USER CODE BEGIN (21) */
/* USER CODE END */
        break;
    }

/* USER CODE BEGIN (22) */
/* USER CODE END */

    _mpuInit_();
	
/* USER CODE BEGIN (23) */
/* USER CODE END */

    _cacheEnable_();

/* USER CODE BEGIN (24) */
/* USER CODE END */


/* USER CODE BEGIN (25) */
/* USER CODE END */

        /* initialize global variable and constructors */
    __TI_auto_init();
/* USER CODE BEGIN (26) */
/* USER CODE END */
    
        /* call the application */
/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
    main();
/* USER CODE BEGIN (27) */
/* USER CODE END */
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
    exit(0);


/* USER CODE BEGIN (28) */
/* USER CODE END */

}

/* USER CODE BEGIN (29) */
/* USER CODE END */

/** @fn void handlePLLLockFail(void)
*   @brief This function handles PLL lock fail.
*/
/* USER CODE BEGIN (30) */
/* USER CODE END */
void handlePLLLockFail(void)
{
/* USER CODE BEGIN (31) */
/* USER CODE END */
	while(1)
	{
		
	}
/* USER CODE BEGIN (32) */
/* USER CODE END */
}
/* USER CODE BEGIN (33) */
/* USER CODE END */

Please send your RTI Blinking App with your Bootloader build I will compare it.

Thanks in advance.

Santhosh

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

Hi Santhosh,

You need to provide exception handlers to handle "Undef", "PAbort", "DAbort" in your Application. If you are sure that the code of bootloader doesn't generate those exceptions, no handlers are needed in bootloader, and you can change the bootloader exception vector table to branch to Application's:

Bootloader sys_intvecs.asm:

b 0x200020-0x8 ,,undefEntry
b 0x200020-0x8 ,,svcEntry
b 0x200020-0x8 ,,prefetchEntry
b 0x200020-0x8 ,,dataEntry

You said the RTI comparators don't work in your Application. Is the CPU jump to application and execute the application code? To check if your application is working or not:

1. Print some debug information to your PC UART terminal

2. Enable ECLK1, and check ECLK1 output using a oscilloscope

3. Toggle a GIO pin, and check the GIO waveform using a oscilloscope

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

exception handlers need to be add in Application or Bootloader HL_sys_intvecs.asm ?

Bootloader:

;-------------------------------------------------------------------------------
; HL_sys_intvecs.asm
;
; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
; 
; 
;  Redistribution and use in source and binary forms, with or without 
;  modification, are permitted provided that the following conditions 
;  are met:
;
;    Redistributions of source code must retain the above copyright 
;    notice, this list of conditions and the following disclaimer.
;
;    Redistributions in binary form must reproduce the above copyright
;    notice, this list of conditions and the following disclaimer in the 
;    documentation and/or other materials provided with the   
;    distribution.
;
;    Neither the name of Texas Instruments Incorporated nor the names of
;    its contributors may be used to endorse or promote products derived
;    from this software without specific prior written permission.
;
;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;
;

    .sect ".intvecs"
    .arm

;-------------------------------------------------------------------------------
; import reference for interrupt routines

    .ref _c_int00
    .ref phantomInterrupt
    .def resetEntry

;-------------------------------------------------------------------------------
; interrupt vectors

resetEntry
        b   _c_int00
undefEntry
        b   #0x200020
    ;    b	undefEntry
svcEntry
        b   #0x200020
     ;   b   svcEntry
prefetchEntry
        b   #0x200020
    ;    b   prefetchEntry
dataEntry
        b   #0x200020
    ;	 b   dataEntry
        b   phantomInterrupt
        ldr pc,[pc,#-0x1b0]
        ldr pc,[pc,#-0x1b0]

    
;-------------------------------------------------------------------------------

Application :

;-------------------------------------------------------------------------------
; HL_sys_intvecs.asm
;
; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
; 
; 
;  Redistribution and use in source and binary forms, with or without 
;  modification, are permitted provided that the following conditions 
;  are met:
;
;    Redistributions of source code must retain the above copyright 
;    notice, this list of conditions and the following disclaimer.
;
;    Redistributions in binary form must reproduce the above copyright
;    notice, this list of conditions and the following disclaimer in the 
;    documentation and/or other materials provided with the   
;    distribution.
;
;    Neither the name of Texas Instruments Incorporated nor the names of
;    its contributors may be used to endorse or promote products derived
;    from this software without specific prior written permission.
;
;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;
;

    .sect ".intvecs"
    .arm

;-------------------------------------------------------------------------------
; import reference for interrupt routines

    .ref _c_int00
    .ref phantomInterrupt
    .def resetEntry

;-------------------------------------------------------------------------------
; interrupt vectors

resetEntry
        b   _c_int00
undefEntry
  ;      b   #0x00200020 ;undefEntry
        b	undefEntry
svcEntry
  ;      b   #0x00200020
        b   svcEntry
prefetchEntry
  ;      b   #0x00200020
  		b   prefetchEntry
dataEntry
   ;     b   #0x00200020 ;
   		b	dataEntry
        b   phantomInterrupt
        ldr pc,[pc,#-0x1b0]
        ldr pc,[pc,#-0x1b0]

    
;-------------------------------------------------------------------------------

In bootloader bl_config.h

#define APP_START_ADDRESS 0x00200020 has defined as 0x00200020 address then

1. Download Application Image To the Internal Flash

Downloaded the Application code then entered

3. Execute The Application Code

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 000114A0

The application is running now !!

it enters to 0x00200020 address then given the same option from bootloader

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 000114A0

BF Application Reprogramming Request: 00
AF Application Reprogramming Request: 00
================== Main Menu ==========================
1. Download Application Image To the Internal Flash
2. Upload The Application Image From the Internal Flash
3. Execute The Application Code
4. Get Bootloader Version
5. Get Device Information
=======================================================

To find the issue I have updated the #define APP_START_ADDRESS 0x00200040 in bl_config.h file of bootloader

then it enters to Application.

Application update status: 5A5A5A5A
Application image address: 00200040
Application image size: 000114A0

The application is running now !!

Now I have connected debugger and checked the code stuck location.

It is in bootloader HL_sys_intvecs.asm file

then step over (F6) then it goes to Application HL_sys_intvecs.asm file bellow.

and again step over (F6) goes to bootloader HL_sys_intvecs.asm file.

Bootloader : HL_sys_link.cmd

VECTORS (X) : origin=0x00000000 length=0x00000020 fill = 0xffffffff
FLASH_API (RX) : origin=0x00000020 length=0x000014E0
FLASH0 (RX) : origin=0x00001500 length=0x001FEB00 vfill = 0xffffffff
FLASH1 (RX) : origin=0x00200000 length=0x001FFFFF vfill = 0xffffffff
/* Bank 7 (128kB, FEE) */
FLASH7 (R) : origin=0xF0200000 length=0x00020000 vfill = 0xffffffff

STACKS (RW) : origin=0x08000000 length=0x00002000
RAM (RW) : origin=0x08002000 length=0x0002EB00

Application : HL_sys_link.cmd

VECTORS (X) : origin=0x00200020 length=0x00000020
/*FLASH0 (RX) : origin=0x00000000 length=0x001FFFEF*/
FLASH1 (RX) : origin=0x00200040 length=0x003FFFFF-0x00200040 /*vfill = 0xffffffff*/
/* Bank 7 (128kB, FEE) */
// FLASH7 (R) : origin=0xF0200000 length=0x00020000 vfill = 0xffffffff
STACKS (RW) : origin=0x08030000 length=0x00001500
RAM (RW) : origin=0x08031500 length=0x0003EB00

How to determine this address for HL_sys_intvecs.asm file

undefEntry
; b #0x200020-0x8 ;undefEntry

What is that - 0x8 in this Address definition?

Please reply as soon as possible .

Thanks in advance

Santhosh

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

Santhosh Chandramohan said:
What is that - 0x8 in this Address definition?

Program Counter (PC) always pointers two instructions beyond the current executed instruction. This is why 0x200020-0x8 is used. If you don't have exception handlers in your application, this change is meaningless.

Santhosh Chandramohan said:
APP_START_ADDRESS 0x00200040 in bl_config.h

If APP_START_ADDRESS is 0x200040, the address for intvec in linker cmd file should be changed to 0x200040 accordingly

VECTORS (X) : origin=0x00200040 length=0x00000020

Please read my notes about how to troubleshooting the abort exceptions

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

QJ Wang said:
If you don't have exception handlers in your application, this change is meaningless.

No exception handlers only RTI compare 0 , RTI compare 3

QJ Wang said:
Please read my notes about how to troubleshooting the abort exceptions

Can you share me the how to troubleshooting the abort exceptions ?

QJ Wang said:
Santhosh Chandramohan said:
APP_START_ADDRESS 0x00200040 in bl_config.h

If APP_START_ADDRESS is 0x200040, the address for intvec in linker cmd file should be changed to 0x200040 accordingly

if APP_START_ADDRESS 0x00200020 in bl_config.h

n bootloader bl_config.h

#define APP_START_ADDRESS 0x00200020 has defined as 0x00200020 address then

1. Download Application Image To the Internal Flash

Downloaded the Application code then entered

3. Execute The Application Code

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 000114A0

The application is running now !!

it enters to 0x00200020 address then given the same option from bootloader

Application update status: 5A5A5A5A
Application image address: 00200020
Application image size: 000114A0

It is jumping back to Bl_main after jumping to Application.

Thanks in advance.

Santhosh

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

My notes:

https://software-dl.ti.com/hercules/hercules_docs/latest/hercules/FAQ/FAQ.html#troubleshooting-abort-exceptions

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

Yes, I have gone through your note regarding the Exceptions.

I have tried to change the name of _c_int00 to _c_int01 in bootloader

After this change, the code always goes to prefetchEntry in HL_sys_intvecs.asm

SPSR_ABT 0x600003F0

M 10000 Mode of ARM: 0x10=User

CPSR 0x600003D7

M 10111 Mode of ARM: 0x17=ABT

CP15_INSTRUCTION_FAULT_STATUS 0x0000000D IFSR [Core]

STATUS 1101 Status[3:0] - 0x0D=Perm

CP15_INSTRUCTION_FAULT_ADDRESS 0xFFFFFFFE IFAR [Core]
Holds address of fault when prefetch abort occurs

If _c_int00 both or normal condition are same in bootloader and Application:

from bootloader to Application is #0x00200020 Address jumps condition but it restarts the bootloader from 0x00000000

Thanks in advance

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

After jumping to Application from bootloader

It is running if i use debugger but the code is not running as it needs and it doesn't enter the RTI interrupt rtiNotification function also.

As per your note regarding exceptions Abort absorbed:

CP15_INSTRUCTION_FAULT_ADDRESS	0x08080000	IFAR [Core]
CP15_INSTRUCTION_FAULT_STATUS	0x00001008	IFSR [Core]
STATUS	1000	0x08=SExt
Abort_Registers
SPSR_ABT	0x4000037F
M	11111	0x1F=SYS
R13_ABT	0x08001400
R14_ABT	0x08080004

Can you please guide to resolve this issue.

Thanks in Advance.

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

In the application main, _enable_IRQ_interrupt_(); function is called because of this function it jumps to bootloader code.

So how to use the RTI interrupt with the bootloader. Can you check it and confirm me as soon as possible ?

Thanks in advance.

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

In the application main, _enable_IRQ_interrupt_(); function is called because of this function it jumps to bootloader code.

So how to use the RTI interrupt in application with _enable_IRQ_interrupt_(); function which trigger to bootloader. Can you check it and confirm me as soon as possible ?

Thanks in advance.

Santhosh

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

Hi Santhosh,

1. Enable the VIM channel for RTI compare interrupt, for example RTI compare 0

2. Enable the RTI compare interrupt

After RTI is initialized (rtiInit()), calling

rtiEnableNotification(rtiREG1, rtiNOTIFICATION_COMPARE0);

will enable the RTI compare 0 notification.

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

Yes, Similarly I have enabled RTI comapre3 in VIM channel

In main code , Without calling _enable_IRQ_interrupt_(); and rtiStartCounter(rtiREG1,rtiCOUNTER_BLOCK1); this two function the interrupt is not triggering in rtiNotification function which is given below.

Thanks in advance

Santhosh.

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

After I have debugged it finally it went to prefetchEntry and checked all the registered.

SPSR_IRQ	0x60000352
M	10010	Mode of ARM: 0x12=IRQ
R13_IRQ	0x08001300
R14_IRQ	0x00011D04
CPSR	0x200003D7
M	10111	Mode of ARM: 0x17=ABT Abort
CP15_INSTRUCTION_FAULT_STATUS	0x0000000D	IFSR [Core]
STATUS	1101	Status[3:0] - 0x0D=Perm
CP15_INSTRUCTION_FAULT_ADDRESS	0xFFFFFFFE	IFAR [Core]

and check the above the message also.

Thanks in advance.

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

I also facing the same issue which is present in this link

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/638874/tms570lc4357-how-to-handle-application-interrupt-with-a-bootloader

Please explain this point the below point.

Pay attention to the code“switch (getResetSource ())....” in the HL_sys_startup.c file.

When the code jump into app from bootloader, the reset source is cleared at bootloader, the interrupt vector initialization and other functions will not be executed, so the interruption in app can not enter.

If this place is not modified, this problem will be encountered.

Please support me as soon as possible.

It is very urgent to fix it

Thanks in advance.

Santhosh

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

The address 0xFFFFFFFE is part of the memory map that is not executable, so the permission fault (0x0000000D) is valid. M[4:0]=10010b shows that the exception occurred when the CPU was processing a service routine for an IRQ. Please check the size of stack allocated for IRQ mode. Do you have an ISR that declares local variables? These use stack. You can increase the available IRQ stack to see if that helps.

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

Santhosh Chandramohan said:
e2e.ti.com/.../quote]
In Application, you don't need to run PBIST, memory initialization, and PLL workaround, PBIST workaround, and CPU selftest. If the application uses the same PLL value, you don't have to run systemInit().

The application don't use reset-source.

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 197036 points

The following is the code (blue) in my application example:

rstSrc = getResetSource();
switch(rstSrc)
{
case POWERON_RESET:

... ...

default:
/* USER CODE BEGIN (21) */

if(rstSrc != POWERON_RESET)
{
_memInit_();
}
_coreEnableEventBusExport_();

if ((esmREG->SR1[2]) != 0U)
{
esmGroup3Notification(esmREG,esmREG->SR1[2]);
}
systemInit();
_coreEnableIrqVicOffset_();
vimInit();
esmInit();

/* USER CODE END */

break;

}

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

Did I need to comment only systemInit(); function in application ?

Thanks in advance

Santhosh.

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

HI Santhosh.,

If you use my example code in default section, you don't need to comment out any other function call.

QJ Wang said:
rstSrc = getResetSource();
switch(rstSrc)
{
case POWERON_RESET:

... ...

... ...

default:
/* USER CODE BEGIN (21) */

if(rstSrc != POWERON_RESET)
{
_memInit_();
}
_coreEnableEventBusExport_();

if ((esmREG->SR1[2]) != 0U)
{
esmGroup3Notification(esmREG,esmREG->SR1[2]);
}
systemInit();
_coreEnableIrqVicOffset_();
vimInit();
esmInit();

/* USER CODE END */

break;

}

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

How to check the stack size for IRQ mode.

All the variables are declared as global variable main file.

Bootloader: link.cmd file

modified Stack below.

After increased

This issue I got.

Bootloader R5_MPU_PMU:

Did I need to modify in Configuration also HelCoGen ?

Thanks in advance.

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

After I have added your code in default case of HL_sys_startup.c in application I have resolved my Power reset issue.

Application is working if it is entered from bootloader every time after power reset.

Entered 3. Execute The Application Code is execute fine every time after power reset, but from application to bootloader it is not jumping fine to 0x00000000 bootloader address.

In all 3 modification of bootloader HL_sys_intvecs.asm file is given below.

1 method of Bootloader HL_sys_intvecs.asm

I got exception in PrefetchEntry of bootloader.

SPSR_ABT	0x6000037F
M	11111	Mode of ARM: 0x1F=SYS
R13_ABT	0x08001400
R14_ABT	0x08080004
CPSR	0x600003D7
M	10111	Mode of ARM: 0x17=ABT
CP15_INSTRUCTION_FAULT_STATUS	0x00001008	IFSR [Core]
STATUS	1000	Status[3:0] - 0x01=Algn
CP15_INSTRUCTION_FAULT_ADDRESS	0x08080000	IFAR [Core]
CP15_AUX_INSTRUCTION_FAULT_STATUS	0x00000000	AIFSR [Core]
CP15_DATA_FAULT_ADDRESS	0x00000000	DFAR [Core]
CP15_DATA_FAULT_STATUS	0x00000000	DFSR [Core]

2. method of bootloader HL_sys_intvecs.asm

In this method I got an exception PrefetchEntry in Application

SPSR_ABT	0x2000037F
M	11111	Mode of ARM: 0x1F=SYS
R13_ABT	0x08001400
R14_ABT	0x08080004
CPSR	0x200003D7
M	10111	Mode of ARM
CP15_INSTRUCTION_FAULT_STATUS	0x00001008	IFSR [Core]
STATUS	1000	Status[3:0] - 0x01=Algn
CP15_INSTRUCTION_FAULT_ADDRESS	0x08080000	IFAR [Core]
CP15_AUX_INSTRUCTION_FAULT_STATUS	0x00000000	AIFSR [Core]
CP15_DATA_FAULT_ADDRESS	0x00000000	DFAR [Core]
CP15_AUX_DATA_FAULT_STATUS	0x00000000	ADFSR [Core]
CP15_SYSTEM_CONTROL	0x8BE5187C	SCTLR [Core]

3 method of Bootloader HL_sys_intvecs.asm

I got exception in PrefetchEntry of bootloader as same as method 1.

SPSR_ABT	0x6000037F
M	11111	Mode of ARM: 0x1F=SYS
R13_ABT	0x08001400
R14_ABT	0x08080004
CPSR	0x600003D7
M	10111	Mode of ARM
CP15_INSTRUCTION_FAULT_STATUS	0x00001008	IFSR [Core]
STATUS	1000	Status[3:0] - 0x01=Algn
CP15_INSTRUCTION_FAULT_ADDRESS	0x08080000	IFAR [Core]
CP15_AUX_INSTRUCTION_FAULT_STATUS	0x00000000	AIFSR [Core]
CP15_DATA_FAULT_ADDRESS	0x00000000	DFAR [Core]
CP15_AUX_DATA_FAULT_STATUS	0x00000000	ADFSR [Core]
CP15_SYSTEM_CONTROL	0x8BE5187C	SCTLR [Core]

Can you please check this and give your feedback

Thanks in advance.

Santhosh.

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

Can you please share your bootloader and application build for my reference which uses the RTI interrupt.

Thanks in advance.

Santhosh

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

Hi Santhosh,

Santhosh Chandramohan said:
Execute The Application Code is execute fine every time after power reset, but from application to bootloader it is not jumping fine to 0x00000000 bootloader address.

It is nice to make the application work. How do you make the execution jump back to bootloader?

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 197036 points

Can you try the following statement to jump to 0x00000000?

((void (*)(void))0x0)();

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

Yes it is the same code which I have used.

#define BOOT_START_ADDRESS 0x00000000

g_ulbootTransferAddress = (uint32_t)BOOT_START_ADDRESS;
((void (*)(void))g_ulbootTransferAddress)();

Vector is 0x00000000

Flash_API 0x00000020

Flash0 : 0x00001500

bootloader link.cmd

STACKS (RW) : origin=0x08000000 length=0x00002000
RAM (RW) : origin=0x08002000 length=0x0002EB00

flashAPI:
{
.\HALCoGen\source\Fapi_UserDefinedFunctions.obj (.text)
.\Boot\bl_flash.obj (.text)
--library = F021_API_CortexR4_BE_L2FMC.lib (.text)
} palign=8 load = FLASH_API, run = RAM, LOAD_START(apiLoadStart), RUN_START(apiRunStart), SIZE(apiLoadSize)

Application link.cmd

#if 1
VECTORS (X) : origin=0x00200020 length=0x00000020
FLASH0 (RX) : origin=0x00000000 length=0x001FFFEF
FLASH1 (RX) : origin=0x00200040 length=0x003FFFFF-0x00200040 /*vfill = 0xffffffff*/
/* Bank 7 (128kB, FEE) */
// FLASH7 (R) : origin=0xF0200000 length=0x00020000 vfill = 0xffffffff
STACKS (RW) : origin=0x08030000 length=0x00002500
RAM (RW) : origin=0x08032500 length=0x0003EB00

Please can you check it and give feedback .

Thanks in advance.

Santhosh

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 197036 points

The instruction in my previous post branches code execution to 0x00000, it doesn't reset the device and device's peripherals.

You can issue a SW reset command to restart the code from bootloader:

systemREG1->SYSECR = (0x10) << 14;

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

Where can I use this SW reset command code in bootloader or application and which c file

systemREG1->SYSECR = (0x10) << 14;

Please feedback it

Thanks in advance

Santhosh

0 QJ Wang over 3 years ago in reply to Santhosh Chandramohan

TI__Guru**** 197036 points

You can issue the SW reset command whenever you need reset.

In Application:

You can replace ((void (*)(void))g_ulbootTransferAddress)(); with systemREG1->SYSECR = (0x10) << 14

In Bootloader:

After the application is loaded to flash, you can issue a SW reset command to restart the code execution.

0 Santhosh Chandramohan over 3 years ago in reply to QJ Wang

Intellectual 391 points

Hi QJ Wang,

After I have replaced systemREG1->SYSECR = (0x10) << 14; with ((void (*)(void))g_ulbootTransferAddress)();

I have got exception dataEntry stuck in HL_sys_intvecs.asm in bootloader

1. method of bootloader HL_sys_intvecs.asm

CPSR	0x600003D7
M	10111	Mode of ARM: 0x17=ABT
SPSR_IRQ	0x000003D2
M	10010	Mode of ARM: 0x12=IRQ,
R13_IRQ	0x08001300
R14_IRQ	0x00011D14

CP15_DATA_FAULT_STATUS	0x00001008	DFSR [Core]
CP15_INSTRUCTION_FAULT_STATUS	0x00000000	IFSR [Core]
CP15_AUX_DATA_FAULT_STATUS	0x00500000	ADFSR [Core]
CP15_AUX_INSTRUCTION_FAULT_STATUS	0x00000000	AIFSR [Core]
CP15_DATA_FAULT_ADDRESS	0xFFF7E404	DFAR [Core]
CP15_INSTRUCTION_FAULT_ADDRESS	0x00000000	IFAR [Core]

2. method of bootloader HL_sys_intvecs.asm

I have got exception dataEntry stuck in HL_sys_intvecs.asm in Application

CPSR	0x600003D7
M	10111	Mode of ARM: 0x17=ABT
SPSR_IRQ	0x000003D2
M	10010	Mode of ARM: 0x12=IRQ,
R13_IRQ	0x08001300
R14_IRQ	0x00011D14
CP15_DATA_FAULT_STATUS	0x00001008	DFSR [Core]
STATUS	1000	Status[3:0] - 0x08=SExt
CP15_INSTRUCTION_FAULT_STATUS	0x00000000	IFSR [Core]
STATUS	0	Status[3:0] - 0x00=BG
CP15_AUX_DATA_FAULT_STATUS	0x00500000	ADFSR [Core]
CP15_AUX_INSTRUCTION_FAULT_STATUS	0x00000000	AIFSR [Core]
CP15_DATA_FAULT_ADDRESS	0xFFF7E404	DFAR [Core]
CP15_INSTRUCTION_FAULT_ADDRESS	0x00000000	IFAR [Core]

Can you please check this and give your feedback

Thanks in advance.

Santhosh.

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

Is it the same issue I am facing in my project ?

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/916063/tms570lc4357-data-abort-exception-after-software-reset/3429400#3429400

Is this changes need to done in both bootloader and application file ?

Can you share this build ?

Attached is my CCS project:

2664.TMS570LC4357_Sergey.zip

Thanks in advance

Santhosh

0 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

1. method Can I use the PLL for Bootloader is Multiplier as 150 and PLL is 300 and Application Multiplier as 120 and PLL is 240

So the GCM for bootloader VCLK1 is 75 and Application VCLK1 is 80

then how to modify the _C_Init00 and default case in HL_sys_startup

and in HL_system.c

2 method

How to use both bootloader and application same Multiplier as 120 and PLL is 240

and GSM VCLK1 is 80

Because this both PLL and VCLK1 are same I getting an issue in Downloading Application bin file stuck in bl_flash.c

while( FAPI_GET_FSM_STATUS != Fapi_Status_Success ); /* don't have to include this one*/ in Fapi_Init and Fapi_BlockProgram function.

Please guide me to use VCLK1 as 80 in application , So I need to modify in bootloader or use different PLL and VCLK1 which is the best approch.

Thanks in advance.

Santhosh

+1 Santhosh Chandramohan over 3 years ago in reply to Santhosh Chandramohan

Intellectual 391 points

Hi QJ Wang,

After I modified the PLL is 240 by Multiplex is 120 and GCM is modified by HCLK Divider is 0 , VCLK1 Divider is 2, VCLK2 and VCLK3 Divider as 0 So VCLK1 is 80 from Bootloader configuration.

Bootloader:

PLL

GCM

After modified the HalCoGen for VCLK1 as 80 for bootloader as per the application VCLK1.

the Download of Application image is stuck in bl_flash.c code

Is it because of the VCLK1 modification ?

Please check and feedback as soon as possible.

Thanks in advance.

Santhosh

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