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Original question:

LP-AM243: MCAN module bit timings configuration and functional clock

LP-AM243: MCAN external timestamp and interface clock

Antonio Di Maggio
Prodigy 30 points
Part Number: LP-AM243
Other Parts Discussed in Thread: SYSCONFIG

Dear TI Experts,

I am dealing with external timestamp configuration for MCAN module on the LPAM243 demo board.

After reading the Technical Reference Manual my understanding is that the external timestamp counter frequency depends on the interface clock (ICLK), which in turns is  MAIN_SYSCLK0/4 configured by PPLCTRL0.

  • How can i calculate ICLK value?
  • Who configure PLLCTRL0? As for the related question SysConfig does not expose any configuration.

Thanks, best regards.

Antonio

  • 0
    TI__Mastermind 29858 points

    Hi Antonio,

    Antonio Di Maggio said:
    How can i calculate ICLK value?

    ICLK is MAIN_SYSCLK0/4. MAIN_SYSCLK0 has the same frquency as MAIN_PLL0_HSDIV0_CLKOUT.

    The PLL0 output frequency FOUTP is calculated using the equation shown in the TRM, Table 5-1344. PLLTS16FFCLAFRACF Output Clocks. FOUTP is then divided down by PLL0_HSDIV0.

    MCU_HFOSC0_CLKOUT is 25 MHz, see Figure 5-676. MAIN Domain PLLs & LP-AM243x schematic.

    Connect to M3 or R5F0_0, and execute the GEL function Get_All_PLL_Configurations. Plug the values reported by the GEL function into the equations.

    FOUTP = (25e6 / 1) * (80 + 0) = 2e9
    MAIN_PLL0_HSDIV02_CLKOUT = 2e9 / 4 = 500e6, 500 MHz

    Antonio Di Maggio said:
    Who configure PLLCTRL0?

    In No-Boot mode, this is handled by DMSC GEL files. In the case of boot, this is handled by DMSC ROM.

    Antonio Di Maggio said:
    As for the related question SysConfig does not expose any configuration.

    MAIN_SYSCLK0 is fixed, so Sysconfig doesn't expose any configuration to the user.

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    Prodigy 30 points

    Hi Frank,

    Tanks for your prompt reply. Still need clarifiaction.

    Frank Livingston said:
    MAIN_SYSCLK0 has the same frquency as MAIN_PLL0_HSDIV0_CLKOUT.

    Where did younfind this information? From Figure 5-676 (MAIN Domain PLLs Integration) this two values look different from each other. More prcisley MAIN_SYSCLK0 looks an ouptput of the PLL controller PLLCTRL0 as described in section 5.4.5.6. ( PLL and PLL Controller Connection)

    Frank Livingston said:
    In No-Boot mode, this is handled by DMSC GEL files. In the case of boot, this is handled by DMSC ROM.

    I am working in OSPI boot mode with the SOC Initialization Binary flashed (SBL NULL) so I suppose the PPL are configured by the DMSC ROM as described in Table 4-34. (MAIN_PLL0). Where i find MAIN_SYSCLCK0 = 500MHz. Is it correct?

    Thanks

    Antonio

  • +1 in reply to Antonio Di Maggio
    TI__Mastermind 29858 points

    Hi Antonio,

    Antonio Di Maggio said:
    Where did younfind this information?

    I relied on internal documentation to come to this conclusion.

    Antonio Di Maggio said:
    Where i find MAIN_SYSCLCK0 = 500MHz. Is it correct?

    Yes, this is correct. Combining the information in Figure 5-676 & Table 4-34, it can be inferred that PLLCTRL0 doesn't divide down MAIN_PLL0_HSDIV0_CLKOUT.

    It seems R5F ROM configures the MAIN domain PLLs, not DMSC ROM. Please see:

    • Figure 4-3: R5 Configures MAIN Domain PLLs
    • Section 4.5 PLL Configuration: The following tables show the HSDIV values that are programmed by the R5 ROM if a boot mode uses it.

    At any rate, the PLL is configured from ROM, and the MAIN_SYSCLK0 frequency should be considered fixed.

    Regards,
    Frank