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FIQ as NMI

Anthony F. Seely
Guru 68930 points

How does the FIQ work as an NMI?

Specifically:

  -> Is the "F" bit in the CPSR tied permanently to enabled?  It seems that it changes from enabled to disabled sometimes; but this would contradict the term 'non-maskable'.

 

->  How does one handle the case where an FIQ interrupt may come in and interrupt another FIQ ISR that is already in progress.  The two need to share the same banked register set; so if you cannot prevent a second FIQ from occurring before the banked registers are saved (normal things you would do to enable nesting IRQs) then doesn't this mean that only one FIQ can be used per program?  

 

  • 0
    Expert 1910 points

    Hi Anthony,

    At least some of your questions are answered in a previous post: http://e2e.ti.com/support/microcontrollers/tms570/f/312/p/59793/218948.aspx#218948

    To answer your first question: Out of reset, both IRQ and FIQ/NMI are disabled. Once the F bit is cleared in the CPSR, FIQ/NMI are enabled and the F bit cannot be set again.

    In response to your second question, one FIQ cannot interrupt another but the second FIQ will be serviced when handling of the first FIQ is completed.

    Regards,

    Richard

     

     

  • 0 in reply to Richard Burke
    TI__Guru 68930 points

    Hi Richard,

    I agree - thanks.  I'd actually read these posts but you need to read pretty carefully.   Sometimes it's mentioned that "F" cannot be set again;

    sometimes it's mentioned that "F" cannot be set again by software 

     

    I found the following description on ARM's website in the Cortex R4 Technical Reference Manual:

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363g/index.html

    Under Programmer's Model -> Exceptions -> Interrupts -> Non Maskable Fast Interrupts

    "When the NMFI bit in the System Control Register is b1:

    • an instruction writing b0 to the CPSR.F bit clears it to b0

    • an instruction writing b1 to the CPSR.F bit leaves it unchanged

    • the CPSR.F bit can be set to b1 only by an FIQ or reset exception entry."

    This agrees with the other posts - but I also infer from these statements that an FIQ could be made nestable by clearing CPSR.F inside the FIQ handler

    (of course after saving context).     I haven't tried the above yet - but probably need to confirm that it works and put more information into the VIM section of the

    TRM regarding 'how to' nest FIQs.