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TMS570LC4357: SCI protocol based communication

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

In HALCoGen Examples for TMS570LC43xx to transmit data over SCI, busy condition is verified first and then the byte has been transmitted by sciSendByte function. Following is the code snipped from the example:

  • while ((UART->FLR & 0x4) == 4); /* wait until busy */
  • sciSendByte(UART,*text++);      /* send out text   */

I have three queries associated with the same:

  1. While ((UART->FLR & 0x4) == 4) line checks the status of SCI Flags Register (SCIFLR). Since the register is logically ANDed with 0x4, is shall be checking 3rd bit from the 32 bit register. Now looking at the register, 3rd bit is “IDLE” that checks whether SCI receiver in idle state or not. My query here is, why do we need to check the receiver state while we are transmitting the data from SCI? Also, the comment reads as wait until busy. Looking at the register configuration, bus busy flag is 4th So, if that’s the purpose to check, shall we not AND logically with 0x8?
  2. Shall we check bus busy flag only or bus busy flag as well as Txbuf empty both?
  3. Instead of writing while ((UART->FLR & 0x4) == 4);, can we use uint32 sciIsIdleDetected ( sciBASE_t *  sci ) or uint32 sciIsTxReady  ( sciBASE_t *  sci )?
  • Hi Harsh,

    While ((UART->FLR & 0x4) == 4) line checks the status of SCI Flags Register (SCIFLR). Since the register is logically ANDed with 0x4, is shall be checking 3rd bit from the 32 bit register. Now looking at the register, 3rd bit is “IDLE” that checks whether SCI receiver in idle state or not. My query here is, why do we need to check the receiver state while we are transmitting the data from SCI? Also, the comment reads as wait until busy. Looking at the register configuration, bus busy flag is 4th So, if that’s the purpose to check, shall we not AND logically with 0x8?

    The SCI receiver and SCI transmitter may each be operated independently or simultaneously in full duplex mode. My understanding is that the you don't need to check the IDLE and BUSY bit before transmitting message. 

    Shall we check bus busy flag only or bus busy flag as well as Txbuf empty both?

    I don't think that checking BUSY is needed before TXing.

  • The HALCoGen generated function sciSendByte already waits until the transmit buffer is empty before sending the byte:

    /* SourceId : SCI_SourceId_005 */
    /* DesignId : SCI_DesignId_005 */
    /* Requirements : HL_CONQ_SCI_SR9 */
    /** @fn void sciSendByte(sciBASE_t *sci, uint8 byte)
    *   @brief Send Byte
    *   @param[in] sci  - sci module base address
    *   @param[in] byte - byte to transfer
    *
    *   Sends a single byte in polling mode, will wait in the
    *   routine until the transmit buffer is empty before sending
    *   the byte.  Use sciIsTxReady to check for Tx buffer empty
    *   before calling sciSendByte to avoid waiting.
    */
    void sciSendByte(sciBASE_t *sci, uint8 byte)
    {
    /* USER CODE BEGIN (9) */
    /* USER CODE END */
    
    	/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
        while ((sci->FLR & (uint32)SCI_TX_INT) == 0U) 
        { 
        } /* Wait */
        sci->TD = byte;
    
    /* USER CODE BEGIN (10) */
    /* USER CODE END */
    }

    Which I think means the example doesn't need the while ((UART->FLR & 0x4) == 4) loop.