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TMS570LC4357: GPIO : No glitch ?

BEGHIN Guillaume
Prodigy 10 points
Part Number: TMS570LC4357

Hello,

I have a design where states of GPIO at voltage rising and release of reset is critical at least on pin A11

This pin has a pull-down at start tup and my first try show me that startup at ambiant temperature is good, there is no glitch.

 Could you confirm me that this comportement may be reproductible even at the two extreme temperature

Yours sincerely

Guillaume

  • 0
    TI__Guru**** 196306 points

    Hi Guillaume,

    The I/O pins are configured as inputs while nPORRST is low and immediately after nPORRST is released. There is no internal glitch filter on N2HET and GIO pins. While nPORRST is low, both the input buffer and output buffer are disabled. 

    BEGHIN Guillaume said:
    This pin has a pull-down at start tup and my first try show me that startup at ambiant temperature is good, there is no glitch.

    Does the glitch occur when the nPORRST is asserted ot when nPORRST is released? Is this signal a input or output before the nPORRST is asserted? Is there a external pull-up or pull-down on A11 pin? 

    IO can likely switch the pin in <1ns if lightly loaded so a short timing might make such a glitch.