TMS570LC4357: STC self test is not getting completed after enabling the test.

Hi,

I am performing the STC self-test in my application as below with the VCLK and HCLK at 90MHz and GCLK1 at 180MHz. The code is taken with reference to the SafeTI Library code. 

*sys2_stc_clk_div = 0x00000000ul;  // CPU Logic BIST Clock Prescalar STCLKDIV of system 2 module = 0 /

// Maximum STC clock rate support at 180 MHz GCLK1 is 90 MHz. Divide GCLK1 by 2 to achieve this  clock rate.
*stcclkdiv = 0x02020000ul;  // STC Clock Divider Register of STC module = 0x02020000 , To run a diagnostic check on the CPU self-test controller

*sys1_esr = (1u << 5u); // Clear CPU RST status bit in the System Exception Status Register in the system module

*stcscscr = 0UL; // Disable the signature compare logic self-check

*stcgcr0 = (*stcgcr0 & 0x0000F8FEul) | ((125ul << 16ul) | 1ul); // Configure STCGCR0 to start the test from interval 0 till 125.

*stctpr = 0xFFFFFFFFul; // Configure maximum time-out period in STCTPR

for (uint32 index = 0UL; index < (64 + (64 * 1U)); index++); // wait for 64 VBUS clock cycles at least, based on HCLK to VCLK ratio

*stcgcr1 &= 0xFFFFF0F0ul; // Clear the bit fields of STCGCR1
*stcgcr1 |= 0x00000500ul; // Select core 1 for self test
*stcgcr1 |= 0x0000000Aul; // Enable the self test run

// Idle the CPU, so that the self-test can start
__asm__ __volatile__ (
	"WFI \n"
	"nop \n"
	"nop \n"
	"nop \n"
	"nop \n"
	"nop \n"
	"nop \n"
	"nop \n"
	"DMB \n"
	"DMB \n"
);

After enabling the test and the assembly instructions are executed, the self-test status is still active where the ST_ACTIVE bit is seen as 0xA in the STCGSTAT register and the TEST_FAIL, TEST_DONE bits are read as 0.

Understood that the WFI instruction is executing as NOP instruction and hence not resetting the CPU. The assembly code is not given to branch to the address within the link register as we need to point to 0x0 after the CPU reset.

Going through the forums of the ARM processor, understood that the interrupts should be disabled before the WFI instruction to keep the CPU in sleep mode.

In the STC self-test, before the WFI instruction is executed the imprecise/asynchronous abort is held pending in the CPSR register due to the operations performed before the self-test. How could I make the interrupt not pending so that the STC self-test could run and then reset the processor using WFI instruction?

Please let us know the issue resolution why the STC self-test is not getting completed with the above code and how can it be done. Is it due to the imprecise/asynchronous abort?  Also kindly confirm if there is anything missed in performing the STC self-test from the above code?

Thank you,

Tirumala.