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TMS570LS1114: MIBSPI Receive interrupt is triggert only once

Part Number: TMS570LS1114

In our application we use two MIBSPI Ports for communication with external device. MIBSPI3 is used for TX data and MIBSPI5 is used for RX data. Both ports are configured in Master mode, so MIBSPI3 uses SIMO[0] for TX and MIBSPI5 uses SOMI[0] for RX. TX is triggered using polling method. RX shall trigger an interrupt as soon as if 6 x 8bit data is received. The data looks proper on both lines (validated with an oscilloscope).

The issue at this point is that I only get a single interrupt after the first message. After that I see the correct data on the oscilloscope but no interrupt is triggered. What could be the problem here?

Regards,

Konstanty

  • Hi Konstanty,

    SPI is a synchronous, full duplex master-slave-based interface. The data from the master or the slave is synchronized on the rising or falling clock edge. Both master and slave can transmit data at the same time. SPI interfaces can have only one master and can have one or multiple slaves. 

    To begin SPI communication, the master must send the clock signal and select the slave by enabling the CS signal. MOSI transmits data from the master to the slave and MISO transmits data from the slave to the master.

    Both ports are configured in Master mode, so MIBSPI3 uses SIMO[0] for TX and MIBSPI5 uses SOMI[0] for RX.

    It is not a correct configuration. You can config either MibSPI3 or MibSPI5 as the master, but not both. For example, MibSPI3 as the master:

    Master                            Slave

    MibSPI3 SIMO  ---->   MibSPI5 SIMO

    MibSPI3 SOMI <----    MibSPI5 SOMI

    In slave size, all the data is copied to TG0 RAM.