Hello,
This is a question regarding processor live lock function of ESM 2.16.
As a following URL is explaining that ESM 2.16 is EVNTBUSm[35](Processor livelock).
There is explained regarding the generating of livelock at section 7.44 and 7.104 of SPNU540A.
We'd like to confirm whether our understanding is correct.
Note) Our understanding is ECC is calculated each 64-bit.
(1) Two single bit errors in a 64-bit unaligned 32-bit Thumb-2 instruction fetch
For example, if MOV instruction is executed from Address of below, the CPU fetch two MOV instructions of 64-bit, and the CPU livelock occur when single bit error is detected both of instructions.
Example of MOV instruction)
00000FFE: MOV R1, #20h ; F04F0120
Address of 64bit including MOV instruction)
00000FF8: 00 00 00 00 00 00 F0 4F (-> single-bit error)
00001000: 01 20 00 00 00 00 00 00 (-> single-bit error)
(2) A single bit error in a load instruction (LDR or LDM) followed by a single bit error in the instruction's data payload
For example, if LDR instruction and its payload is executed from address of below, the CPU livelock occur when single bit error is detected both of LDR instruction and its payload.
Example of LDR instruction)
00001000: MOV R1, #20h ; E3A01020
00001004: LDR R2, [R1] ; E5912000
Address of 64-bit including LDR instruction and payload)
00000020: 01 23 45 67 89 AB CD EF (-> single-bit error)
...
00001000: E3 A0 10 00 E5 91 20 00 (-> single-bit error)
Is our understanding correct?
In addition, if you know another factor of generating ESM 2.16, could you please tell me about?
Thanks,
Sho
